Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Three Dimensional Integration (3DI) of semiconductor circuit layers: new devices and fabrication process

The device density of Integrated Circuits (ICs) manufactured by current VLSI technology is reaching it\u27s theoretical limit. Nevertheless, the demand for integration of more devices per chip is growing. To accommodate this need three main possibilities can be explored: Wafer Scale Integration (WSI), Ultra Large Scale Integration (ULSI), and Three Dimensional Integration (3DI). A brief review of these techniques along with their comparative advantages and disadvantages is presented. It has been concluded that 3DI technology is superior to others. Therefore, an attempt is made to develop a viable fabrication process for this technology. This is done by first reviewing the current technologies that are utilized for fabrication of Integrated Circuits (ICs) and their compatibility with 3DI stringent requirements.;Based on this review, a set of fabrication procedure for realization of 3DI technology, are presented in chapter 3. In Chapter 1 the compatibility of the currently used devices, such as BJTs and FETS, with 3DI technology is examined. Moreover, a new active device is developed for 3DI technology to replace BJTs and FETs in circuits. This new device is more compatible to the constrains of 3DI technology. Chapter 2 is devoted to solving the overall problems of 3DI circuits. The problem of heat and power dispassion and signal coupling (Cross-Talk) between the layers are reviewed, and an inter-layer shield is proposed to overcome these problems. The effectiveness of such a thin shield is considered theoretically. In Chapter 3 a fabrication process for 3DI technology is proposed. This is done after a short analysis of previous attempts in developing 3DI technologies.;Chapter 4 focuses on analog extension of 3DI technology. Moreover, in this chapter microwave 3DI circuits or 3DI MMIC is investigated. Practical considerations in choice of material for the proposed device is the subject of study in Chapter 5. Low temperature ohmic contact and utilization of metal-silicides for the proposed device are considered in this chapter. Finally in Chapter 6 various computer verifications for this work is presented, and in Chapter 7 experimental results to support this work is included

Downscaling of 0.35 J.lm to 0.25 J.lm CMOS Transistor by Simulation

Silicon (Si) based integrated circuit (IC) has become the backbone of today's semiconductor world with MOS transistors as its fundamental building blocks. The integrated circuit complexity has moved from the early small-scale integration (SSI) to ultra-large-scale integration (ULSI) that can accommodate millions of transistors on a single chip. This evolution is primarily attributed to the concept of device miniaturization. The resulting scaledown devices do not only improve the packing density but also exhibit enhanced performance in terms of faster switching speed and lower power dissipation. The objective of this work is to perform downscaling of 0.35 Jll11 to 0.25 Jll11 CMOS transistor using Silvaco 2-D ATHENA and ATLAS simulation tool. A "two-step design" approach is proposed in this work to study the feasibility of miniaturization process by scaling method. A scaling factor, K of 1.4 (derived from direct division of 0.35 with 0.25) is adopted for selected parameters. The first design step involves a conversion of the physical data of 0.35 Jll11 CMOS technology to the simulated environment, where process recipe acquired from UC Berkeley Microfabrication Lab serves as the design basis. The electrical data for the simulated structure of 0.35 11m CMOS was extracted with the use of the device simulator. Using the simulated, optimized 0.35 Jll11 structure, downscaling to a smaller geometry of 0.25 Jll11 CMOS transistor was carried out and subsequent electrical characterization was performed in order to evaluate its performance. Parameters that are monitored to evaluate the performance of the designed 0.25 Jll11 CMOS transistor include threshold voltage (VtJJ, saturation current (ldsaJ, off-state leakage current (Ion) and subthreshold swing (SJ. From the simulation, the V1h obtained is of 0.51 V and -0.4 V for NMOS and PMOS respectively, with a difference of 15%-33% as compared to other reported work. However, for results of Idsat. the values obtained which is of 296 ~-tAIJll11 for NMOS and 181 J.lA/Jll11 for PMOS is much lower than other reported work by 28%-50%. This is believed to be due to direct scaling of 0.25 Jll11 transistor from the 0.35 11m geometry without alterations on the existing structure. For Ioffand St. both results show a much better value as compared to other work. I off obtained which is of <1 0 pA/J.lm is about 80%-96% lower than the maximum allowable specification. As for S1, the values obtained which is <90 mY/dec is only within 5% differences as compared to specification. In overall, these results (except for Idsat) accepted values for the particular 0.25 J..Lm technology. From this work, the capability to perform device miniaturization from 0.35 J..Lffi to 0.25 J..Lffi has been developed. This is achieved by acquiring the technical know-how on the important aspects of simulation required for successful simulation of 0.35 J..Lffi technology. Ultimately, the outcome of this work which is a simulated 0.25 J..Lm CMOS transistor can be used as a basis for scaling down to a much smaller device, namely towards 90-nrn geometry

Plasma induced damage to Si and SiGe devices and materials

This thesis studied the plasma-induced damage to Si and strained Si1-xGex, and the resulting change in device characteristics. The energetic particles (ions, electrons and photons) in plasma reactor present a potentially hostile environment for processing VLSI devices. An inductively coupled plasma (ICP) reactor was used to study its damage effects to thin gate oxides. Electrical characterizations by C-V, ramped voltage breakdown (RVB) and deep-level transient spectroscopy (DLTS) measurement, and x-ray photoelectron spectroscopy (XPS) analysis were employed to investigate the damages to thin gate oxides and Si/SiO2 interface. The shift of flat band voltage, the reduction of breakdown voltage and the creation of high interface trap density were found to be in good agreement with the creation of suboxidation states at Si/SiO2 interface. It is observed that device damage is well associated with the reactor operating conditions. The major mechanism responsible for damage appeared to be high energy electron charging which occurred when only the ICP power was activated, without any rf bias to the wafercarrying electrode. Energetic particle bombardment damage was dominant when the wafer-carrying electrode\u27was biased and the damage was considerably higher for rf bias power grater than 35W. The effect of plasma processing to the strained Si1-xGex layer of p+ - n diode has been investigated. The effect of SF6 plasma, used to etch an overlying Si film stopping at the strained Si1-xGex film, on the electrical properties of an underlying Si1-xGex/Si heterojunction device was studied. The changes of C-V and I-V characteristics, such as higher depletion capacitance and lower diffusion current were attributed to ion bombardment and radiation-induced bonding change, such as creation of interface charges and recombination centers. The TEM analysis revealed the dislocation loops in Si/Si1-xGex/Si outside the aluminum contact region due to the ion bombardment stress. The O2 plasma ashing has moderate effect to Si1-xGex device when the device was protected by aluminum contact layer. The C-V profiling techniques on SiGe MOS structures were used to investigate the change of valence band discontinuity (ΔEv) at the Si/SiGe interface before and after plasma exposure and high temperature annealing. Wet and plasma etched samples were annealed at 500, 600, 700 and 800°C for 60 seconds. It was observed that the accuracy of extracting the changes of ΔEv using the C-V profiling was strongly influenced by the release of electrons from the traps at SiO2/Si interface, which were created during the low-pressure CVD SiO2, deposition. The device simulations have been used to confirm this finding. By carefully analyzing the C-V profile at slight depletion region the band gap modifications at back Si/SiGe interface due to process-induced damage could be evaluated. The dry etched sample was partially relaxed after 700°C annealing while wet etched sample was partially relaxed after 800°C annealing. Dry etched sample demonstrated a faster relaxation mechanism as compared to its wet etched counterpart due to the creation of dislocation loops by dry etching process. The C-V method is a simple, fast and efficient approach to estimate any band-gap modification in SiGe due to process-induced damage, but the measurements and simulations in slight depletion region should be carried out with special care and high resolution

Conference of Microelectronic Research 1997

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