Silicon (Si) based integrated circuit (IC) has become the backbone of today's semiconductor
world with MOS transistors as its fundamental building blocks. The integrated circuit
complexity has moved from the early small-scale integration (SSI) to ultra-large-scale
integration (ULSI) that can accommodate millions of transistors on a single chip. This
evolution is primarily attributed to the concept of device miniaturization. The resulting scaledown
devices do not only improve the packing density but also exhibit enhanced
performance in terms of faster switching speed and lower power dissipation. The objective of
this work is to perform downscaling of 0.35 Jll11 to 0.25 Jll11 CMOS transistor using Silvaco
2-D ATHENA and ATLAS simulation tool. A "two-step design" approach is proposed in this
work to study the feasibility of miniaturization process by scaling method. A scaling factor, K
of 1.4 (derived from direct division of 0.35 with 0.25) is adopted for selected parameters. The
first design step involves a conversion of the physical data of 0.35 Jll11 CMOS technology to
the simulated environment, where process recipe acquired from UC Berkeley
Microfabrication Lab serves as the design basis. The electrical data for the simulated
structure of 0.35 11m CMOS was extracted with the use of the device simulator. Using the
simulated, optimized 0.35 Jll11 structure, downscaling to a smaller geometry of 0.25 Jll11
CMOS transistor was carried out and subsequent electrical characterization was performed in
order to evaluate its performance. Parameters that are monitored to evaluate the performance
of the designed 0.25 Jll11 CMOS transistor include threshold voltage (VtJJ, saturation current
(ldsaJ, off-state leakage current (Ion) and subthreshold swing (SJ. From the simulation, the V1h
obtained is of 0.51 V and -0.4 V for NMOS and PMOS respectively, with a difference of
15%-33% as compared to other reported work. However, for results of Idsat. the values
obtained which is of 296 ~-tAIJll11 for NMOS and 181 J.lA/Jll11 for PMOS is much lower than
other reported work by 28%-50%. This is believed to be due to direct scaling of 0.25 Jll11
transistor from the 0.35 11m geometry without alterations on the existing structure. For Ioffand
St. both results show a much better value as compared to other work. I off obtained which is of
<1 0 pA/J.lm is about 80%-96% lower than the maximum allowable specification. As for S1,
the values obtained which is <90 mY/dec is only within 5% differences as compared to
specification. In overall, these results (except for Idsat)
accepted values for the particular 0.25 J..Lm technology. From this work, the capability to
perform device miniaturization from 0.35 J..Lffi to 0.25 J..Lffi has been developed. This is
achieved by acquiring the technical know-how on the important aspects of simulation
required for successful simulation of 0.35 J..Lffi technology. Ultimately, the outcome of this
work which is a simulated 0.25 J..Lm CMOS transistor can be used as a basis for scaling down
to a much smaller device, namely towards 90-nrn geometry
