Acceleration of parasitic multistatic radar system using GPGPU

This dissertation details the implementation of PMR [Parasitic Multistatic Radar] signal processing chain in the GPGPU [General Purpose Graphic Processing Units] platform. The primary objective of the project is to accelerate the signal processing chain without compromising the algorithm efficiency and to prove that GPGPUs are a promising platform for parasitic radar signal processing

Synthetic Aperture Radar Signal Processing using GPGPU

In this work an effcient parallel implementation of the Chirp Scaling Algorithm (CSA) for Synthetic Aperture Radar (SAR) processing is presented. The architecture selected for the implementation is General Purpose Graphic Processing Unit (GPGPU), as it is well suited for scientific applications and real time implementation of algorithms. The analysis of a first implementation led to several improvements which resulted in an important final speedup. Details of the issues found are explained, and the performance improvement of their correction explicitly shown

A High-Speed Multi-Purpose Software Defined Radar for Near-Field Applications

Software Defined Radar (SDRadar) is a unique radar system, where most of its processing, like filtering, correlation, signal generation etc. is performed by software. This means SDRadar can be flexibly deployed for different purposes and with a relative short development process. In this paper, we present a generic SDRadar system that can operate in different setups for near-field monitoring applications. Practical solutions for traditional limitations in SDRadar and high sampling rates are introduced, and its performance is demonstrated using a commercial universal software radio peripheral (USRP) device with four synchronized receiving channels and a maximum sampling rate of 100MHz. Additionally, a GPU accelerator has been implemented to deal with the high sampling rate. Three different setups have been tested to demonstrate the feasibility of the propose SDRadar system with distributed nodes, vertically positioned nodes and a miniature scenario. Recorded Doppler signatures have shown the proposed SDRadar can effectively capture the body and hand gestures. Such results can be used in a range of applications such as eHealth, human-machine interaction and indoor tracking

Design of high‐speed software defined radar with GPU accelerator

Software defined radar (SDRadar) systems have become an important area for future radar development and are based on similar concepts to Software defined radio (SDR). Most of the processing like filtering, frequency conversion and signal generation are implemented in software. Currently, radar systems tend to have complex signal processing and operate at wider bandwidth, which means that limits on the available computational power must be considered when designing a SDRadar system. This paper presents a feasible solution to this potential limitation by accelerating the signal processing using a GPU to enable the development of a high speed SDRadar system. The developed system overcomes the limitation on the processing speed by CPU-only, and has been tested on three different SDR devices. Results show that, with GPU accelerator, the processing rate can achieve up to 80 MHz compared to 20 MHz with the CPU-only. The high speed processing makes it possible to run in real-time and process full bandwidth across the WiFi signal acquired by multiple channels. The gains made through porting the processing to the GPU moves the technology towards real-world application in various scenarios ranging from healthcare to IoT, and other applications that required significant computational processing

Embedded System Optimization of Radar Post-processing in an ARM CPU Core

Algorithms executed on the radar processor system contributes to a significant performance bottleneck of the overall radar system. One key performance concern is the latency in target detection when dealing with hard deadline systems. Research has shown software optimization as one major contributor to radar system performance improvements. This thesis aims at software optimizations using a manual and automatic approach and analyzing the results to make informed future decisions while working with an ARM processor system. In order to ascertain an optimized implementation, a question put forward was whether the algorithms on the ARM processor could work with a 6-antenna implementation without a decline in the performance. However, an answer would also help project how many additional algorithms can still be added without performance decline. The manual optimization was done based on the quantitative analysis of the software execution time. The manual optimization approach looked at the vectorization strategy using the NEON vector register on the ARM CPU to reimplement the initial Constant False Alarm Rate(CFAR) Detection algorithm. An additional optimization approach was eliminating redundant loops while going through the Range Gates and Doppler filters. In order to determine the best compiler for automatic code optimization for the radar algorithms on the ARM processor, the GCC and Clang compilers were used to compile the initial algorithms and the optimized implementation on the radar post-processing stage. Analysis of the optimization results showed that it is possible to run the radar post-processing algorithms on the ARM processor at the 6-antenna implementation without system load stress. In addition, the results show an excellent headroom margin based on the defined scenario. The result analysis further revealed that the effect of dynamic memory allocation could not be underrated in situations where performance is a significant concern. Additional statements from the result demonstrated that the GCC and Clang compiler has their strength and weaknesses when used in the compilation. One limiting factor to note on the optimization using the NEON register is the sample size’s effect on the optimization implementation. Although it fits into the test samples used based on the defined scenario, there might be varying results in varying window cell size situations that might not necessarily improve the time constraints

Verification and Calibration of the ICEBEAR Radar through GPU Acceleration, Noise Characterization and Calculation, and Radio Galaxy Phase Calibration

The research performed for this thesis focused on verifying, quantifying, calibrating, and improving the Ionospheric Continuous Wave (CW) E-region Bi-static Radar (ICEBEAR) data observations and quality. Graphical processing unit (GPU) acceleration was used to improve the computation speed of ICEBEAR data analysis. The ICEBEAR noise floor was studied to better understand the ICEBEAR noise environment and verify the signal to noise ratio (SNR), which affects all ICEBEAR data products. Finally, a calibration method using the radio galaxy Cygnus~A was developed to enable improved phase calibration of the ICEBEAR receiver antennas. GPUs enable high computational throughput through the use of parallel processing and specific hardware design. This part of my research used the properties of GPUs to accelerate the data analysis of ICEBEAR to be 48 times faster than the original processing capability, enabling real-time analysis of ICEBEAR data. The current noise calculation technique of taking the median power calculation of the ICEBEAR field of view is reasonable, but it is recommended that ICEBEAR switch to using an average of the furthest ranges measured by the radar. The dominant noise sources in the radar changes based on ionospheric activity, where self-clutter dominates during active periods and cosmic noise dominates during quite periods. This impacts the computation of the SNR data product and is better quantified by a far range average for all 45 baselines in the ICEBEAR radar. The detection of Cygnus~A during quiet ionospheric periods was used to calculate phase self-calibrations for the radar by comparing the measured phase difference between antennas to the expected theoretical phase difference of Cygnus~A. The technique is shown to generate similar and complementary results to the current spectrum analyzer calibration technique. Future improvements to ICEBEAR imaging analysis and future research into the improved observation of Cygnus~A will allow this new phase self-calibration method to be actively used for ICEBEAR

A scalable real-time processing chain for radar exploiting illuminators of opportunity

Includes bibliographical references.This thesis details the design of a processing chain and system software for a commensal radar system, that is, a radar that makes use of illuminators of opportunity to provide the transmitted waveform. The stages of data acquisition from receiver back-end, direct path interference and clutter suppression, range/Doppler processing and target detection are described and targeted to general purpose commercial off-the-shelf computing hardware. A detailed low level design of such a processing chain for commensal radar which includes both processing stages and processing stage interactions has, to date, not been presented in the Literature. Furthermore, a novel deployment configuration for a networked multi-site FM broadcast band commensal radar system is presented in which the reference and surveillance channels are record at separate locations

Passive radar parallel processing using General-Purpose computing on Graphics Processing Units

In the paper an implementation of signal processing chain for a passive radar is presented. The passive radar which was developed at the Warsaw University of Technology, uses FM radio and DVB-T television transmitters as "illuminators of opportunity". As the computational load associated with passive radar processing is very high, NVIDIA CUDA technology has been employed for effective implementation using parallel processing. The paper contains the description of the algorithms implementation and the performance results analysis