Reconfiguration based built-in self-test for analogue front-end circuits

Previous work has shown that it is feasible to implement a fully digital test evaluation function to realise partial self-test on an automatic gain control circuit (AGC). This paper extends the technique to INL, DNL, offset & gain error testing of analogue to digital converters (ADC's). It also shows how the same function can be used to test an AGC / ADC pair. An extension to full self-test is also proposed by the on-chip generation of input stimuli through reconfiguration of existing functions

Analogue integrated circuits design-for-testability flow oriented onto OBIST strategy

© Kaunas University of Technology. Oscillation Built-In Self-Test (OBIST) strategy allows to avoid the using complex, expensive generators of input test signals during testing, and uses the oscillation frequency generated at the output of the circuit after reconfiguring into oscillator as a controlled parameter. There configuration subcircuit forms an oscillator from the original circuit in the test mode and requires an additional but insignificant area of the chip, especially against the background of stable increasing the scale of integration for the state-of-the-art integrated technologies. Selection of the efficient type of reconfiguration the original circuit into oscillator and implementation of corresponding test circuitry are the most important tasks, which, as rule, are solved nowadays based on experience of designers without automation and therefore restrict to wide use of the OBIST concept. The paper is mainly focused on the task of design-for-testability (DFT) automation with emphasis on the OBIST strategy for analog integrated circuits (IC). The design procedures according to DFT flow are proposed. Three possible structural solutions for reconfiguration of original circuit into an oscillator are considered. The necessary conditions for stability analysis of reconfigured circuit are presented. The stage of a numerical estimating the transient time before the steady-state operation after reconfiguration of original circuit into an oscillator ensuring definition of the start time point for correct calculating the oscillation frequency is proposed. The set of rules for each structural solution for reconfiguration is prepared as the formal procedures, which can support the automation during the DFT flow. The efficiency of the proposed DFT flow is demonstrated for analog circuits, for which the reconfiguration subcircuits were obtained in an automated way during design-for-testability, as well as the fault simulation has been performed. The experimental results for all cases showed the adequacy of oscillation frequency for revealing both catastrophic and parametric faults. Fault coverage for considered set of faults has consisted up to 100%

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Analog System-on-a-Chip with Application to Biosensors

This dissertation facilitates the design and fabrication of analog systems-on-a-chip (SoCs). In this work an analog SoC is developed with application to organic fluid analysis. The device contains a built-in self-test method for performing on-chip analysis of analog macros. The analog system-on-a-chip developed in this dissertation can be used to evaluate the properties of fluids for medical diagnoses. The research herein described covers the development of: analog SoC models, an improved set of chemical sensor arrays, a self-contained system-on-a-chip for the determination of fluid properties, and a method of performing on-chip testing of analog SoC sub-blocks

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

On-chip evaluation of oscillation-based-test output signals for switched-capacitor circuits

This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approac

A new BIST scheme for low-power and high-resolution DAC testing

A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed

Conception pour la testabilité des systèmes biomédicaux implantables

Architecture générale des systèmes implantables -- Principes de stimulation électrique -- Champs d'application des systèmes implantables -- Les particularités des circuits implantables -- Tendance future -- Conception pour la testabilité de la partie numérique des circuits implantables -- "Desigh and realization of an accurate built-in current sensor for Iddq testing and power dissipation measurement -- Conception pour la testabilité de la partie analogique des circuits implantables -- BIST for digital-to-analog and Analogo-to-digital converters -- Efficient and accurate testing of analog-to-digital converters using oscillation test method -- Design for testability of Embedded integrated operational amplifiers -- Vérification des interfaces bioélectroniques des systèmes implantables -- Monitorin the electrode and lead failures in implanted microstimulators and sensors -- Capteurs de température intégrés pour la vérification de l'état thermique des puces dédiées -- Built-in temperature sensors for on-line thermal monitoring of microelectronic structures -- Un protocole de communication fiable pour la programmation et la télémétrie des système implantables -- A reliable communication protoco for externally controlled biomedical implanted devices