3,296 research outputs found
Efficient optimization of the integrity behavior of analog nonlinear devices using surrogate models
A novel technique to analyze and optimize the integrity behavior of nonlinear analog devices in the presence of noise is proposed. The technique leverages surrogate models, as such reducing the simulation time, avoiding time-consuming and expensive measurements after tape-out and hiding the original netlist of the circuit, while maintaining high accuracy. Easy integration of the surrogates into a circuit simulator together with pertinent subcircuits representing, e. g., board and package, allows mimicking the integrity behavior of a complete setup while still being in the design phase. In this contribution, the method is applied to a case study, being a voltage regulator designed for automotive applications
Harmonic balance surrogate-based immunity modeling of a nonlinear analog circuit
A novel harmonic balance surrogate-based technique to create fast and accurate behavioral models predicting, in the early design stage, the performance of nonlinear analog devices during immunity tests is presented. The obtained immunity model hides the real netlist, reduces the simulation time, and avoids expensive and time-consuming measurements after tape-out, while still providing high accuracy. The model can easily be integrated into a circuit simulator together with additional subcircuits, e.g., board and package models, as such allowing to efficiently reproduce complete immunity test setups during the early design stage and without disclosing any intellectual property. The novel method is validated by means of application to an industrial case study, being an automotive voltage regulator, clearly showing the technique's capabilities and practical advantages
Enabling High-Dimensional Hierarchical Uncertainty Quantification by ANOVA and Tensor-Train Decomposition
Hierarchical uncertainty quantification can reduce the computational cost of
stochastic circuit simulation by employing spectral methods at different
levels. This paper presents an efficient framework to simulate hierarchically
some challenging stochastic circuits/systems that include high-dimensional
subsystems. Due to the high parameter dimensionality, it is challenging to both
extract surrogate models at the low level of the design hierarchy and to handle
them in the high-level simulation. In this paper, we develop an efficient
ANOVA-based stochastic circuit/MEMS simulator to extract efficiently the
surrogate models at the low level. In order to avoid the curse of
dimensionality, we employ tensor-train decomposition at the high level to
construct the basis functions and Gauss quadrature points. As a demonstration,
we verify our algorithm on a stochastic oscillator with four MEMS capacitors
and 184 random parameters. This challenging example is simulated efficiently by
our simulator at the cost of only 10 minutes in MATLAB on a regular personal
computer.Comment: 14 pages (IEEE double column), 11 figure, accepted by IEEE Trans CAD
of Integrated Circuits and System
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology
In this paper, physical implementations and measurement results are presented for several Voltage Controlled Oscillators that were designed using a fully-automated, layout- and variability-aware optimization-based methodology. The methodology uses a highly accurate model, based on machine-learning techniques, to characterize inductors, and a multi-objective optimization algorithm to achieve a Pareto-optimal front containing optimal circuit designs offering different performance trade-offs. The final outcome of the proposed methodology is a set of design solutions (with their GDSII description available and ready-to-fabricate) that need no further designer intervention. Two key elements of the proposed methodology are the use of an optimization algorithm linked to an off-the-shelf simulator and an inductor model that yield EM-like accuracy but with much shorter evaluation times. Furthermore, the methodology guarantees the same high level of robustness against layout parasitics and variability that an expert designer would achieve with the verification tools at his/her disposal. The methodology is technology-independent and can be used for the design of radio frequency circuits. The results are validated with experimental measurements on a physical prototype
Design Optimization of Full-Wave EM Models by Low-Order Low-Dimension Polynomial Surrogate Functionals
A practical formulation for EM-based design optimization of high-frequency circuits using simple polynomial surrogate functionals is proposed in this paper. Our approach starts from a careful selection of design variables and is based on a closed-form formulation that yields global optimal values for the surrogate model weighting factors, avoiding a large set of expensive EM model data, and resulting in accurate low-order low-dimension polynomials interpolants that are used as vehicles for efficient design optimization. Our formulation is especially suitable for EM-based design problems with no equivalent circuital models available. The proposed technique is illustrated by the EM-based design optimization of a Ka-band substrate integrated waveguide (SIW) interconnect with conductor-backed coplanar waveguide (CBCPW) transitions, a low crosstalk PCB microstrip interconnect structure with guard traces, and a 10-40 GHz SIW interconnect with microstrip transitions on a standard FR4-based substrate. Three commercially available full-wave EM solvers are used in our examples: CST, Sonnet and COMSOL
A Review of Bayesian Methods in Electronic Design Automation
The utilization of Bayesian methods has been widely acknowledged as a viable
solution for tackling various challenges in electronic integrated circuit (IC)
design under stochastic process variation, including circuit performance
modeling, yield/failure rate estimation, and circuit optimization. As the
post-Moore era brings about new technologies (such as silicon photonics and
quantum circuits), many of the associated issues there are similar to those
encountered in electronic IC design and can be addressed using Bayesian
methods. Motivated by this observation, we present a comprehensive review of
Bayesian methods in electronic design automation (EDA). By doing so, we hope to
equip researchers and designers with the ability to apply Bayesian methods in
solving stochastic problems in electronic circuits and beyond.Comment: 24 pages, a draft version. We welcome comments and feedback, which
can be sent to [email protected]
Tensor Computation: A New Framework for High-Dimensional Problems in EDA
Many critical EDA problems suffer from the curse of dimensionality, i.e. the
very fast-scaling computational burden produced by large number of parameters
and/or unknown variables. This phenomenon may be caused by multiple spatial or
temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit
simulation), nonlinearity of devices and circuits, large number of design or
optimization parameters (e.g. full-chip routing/placement and circuit sizing),
or extensive process variations (e.g. variability/reliability analysis and
design for manufacturability). The computational challenges generated by such
high dimensional problems are generally hard to handle efficiently with
traditional EDA core algorithms that are based on matrix and vector
computation. This paper presents "tensor computation" as an alternative general
framework for the development of efficient EDA algorithms and tools. A tensor
is a high-dimensional generalization of a matrix and a vector, and is a natural
choice for both storing and solving efficiently high-dimensional EDA problems.
This paper gives a basic tutorial on tensors, demonstrates some recent examples
of EDA applications (e.g., nonlinear circuit modeling and high-dimensional
uncertainty quantification), and suggests further open EDA problems where the
use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and
System
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