Minimizing Channel Density with Movable Terminals

We give algorithms to minimize density for VLSI channel routing problems with terminals that are movable subject to certain constraints. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, we improve previous results for running time and space by a factor of L/\lgn and L, respectively, where L is the channel length, and n is the number of terminals

Movable wall and system with environmental condition optimisation functions

The present invention relates to the field of control of indoor environmental conditions. In particular, the invention relates to a movable wall with environmental condition optimisation functions, as well as a system comprising such movable wall, and an environmental condition optimisation method

A review of conducting polymers in electrical contact applications

A review of recent developments in fretting studies in electrical contacts is presented, focusing on developments in conducting polymer surfaces. Fretting is known to be a major cause of contact deterioration and failure; commonly exhibited as the contact resistance increases from a few milliohms, in the case of a new metallic contacts, to in excess of several ohms for exposed contacts. Two technologies are discussed; firstly extrinsically conducting polymer (ECP), where highly conductive interconnects are formed using metallized particles embedded within a high temperature polymer compound, and secondly; intrinsically conducting polymers (ICPs) are discussed. These latter surfaces are new developments which are beginning to show potential for the application discussed. This paper presents the work on the ICPs using poly(3,4-ethylenedioxythiophene)/poly(4-styrenesulfonate) (PEDOT /PSS) and its blends from secondary doping of dimethylformamide (DMF)PEDOT/PSS. Two different processing techniques namely dropcoating and spin coating have been employed to develop test samples and their functionality were assessed by two independent studies of temperature and fretting motion. The review leads to a number of recommendations for further studies into the application of conducting polymers for contacts with micro-movement.<br/

A complete design path for the layout of flexible macros

XIV+172hlm.;24c

Стенд остаточного складання автомобільних дверних панелей

Розробити оптимальну систему програмного і апаратного забезпечення стенду остаточного складання автомобільних дверних панелей, якабуде відповідати представленим вимогам швидкості, якості та безпеки виробничого процесу

PROGRAMMABLE ROBOTIC ARM REPLICATING MASTER ROBOT

A Robotic arm is a robotic manipulator usually programmable, with similar functions to a human arm. Servomotor is used for joint rotation .it has about same number of degree of freedom as in human arm. Humans pick up with outthinking about the steps invalid. In an order for a robot or a robotic arm to pick or more something. Some has to tell it to perform several actions in a particular order from moving the arm, to rotating the wrist to opening or closing the hand are finger. So we do control each joint through computer interface. The arm has 8 servo mechanisms for precise control of angular poison. The RC servomotors usually have a rotation limit from 90 to 180 degrees. Bur servo doesn’t rotate continually. They are used in robotic arm and legs, sensor scanner and in RC toys. It can be used for performing take like welding, gripping, spinning in space. In medical science (neurone). The arm is for manufacturing units decreasing human labour. Reducing human stress nothing but workload

Efficient quadratic placement for FPGAs.

Field Programmable Gate Arrays (FPGAs) are widely used in industry because they can implement any digital circuit on site simply by specifying programmable logic and their interconnections. However, this rapid prototyping advantage may be adversely affected because of the long compile time, which is dominated by placement and routing. This issue is of great importance, especially as the logic capacities of FPGAs continue to grow. This thesis focuses on the placement phase of FPGA Computer Aided Design (CAD) flow and presents a fast, high quality, wirelength-driven placement algorithm for FPGAs that is based on the quadratic placement approach. In this thesis, multiple iterations of equation solving process together with a linear wirelength reduction technique are introduced. The proposed algorithm efficiently handles the main problems with the quadratic placement algorithm and produces a fast and high quality placement. Experimental results, using twenty benchmark circuits, show that this algorithm can achieve comparable total wirelength and, on average, 5X faster run time when compared to an existing, state-of-the-art placement tool. This thesis also shows that the proposed algorithm delivers promising preliminary results in minimizing the critical path delay while maintaining high placement quality.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .X86. Source: Masters Abstracts International, Volume: 44-04, page: 1946. Thesis (M.A.Sc.)--University of Windsor (Canada), 2005

On the design and implementation of a wafer yield editor

An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and is able to predict wafer yields via simple simulation tools. An analysis approach based on site yields makes the system independent of the product and of the technology. The analysis technique makes it possible to investigate the effects of both correlated and uncorrelated sources of yield loss. The statistical information obtained can be used to study changes in the technological process. Graphical displays in the form of wafer maps are used to represent the spatial distribution of dice in the wafer. Capabilities for such as radial and angular distribution analyses, among others, are provided to examine data, and hypothetical wafer maps are created to visualize and predict simulated wafer yield

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon