Method for PID-tuning via feedback control system pole placement

Pole placement is the only PID-tuning technic that allows one to obtain a control system with desired, and, moreover, highly predictable performance and control quality. Number of controller tuning parameters is equal to number of poles closed-loop poles it can precicely place, so that PID-controller can place exactly three poles, and PI- can place only two. For this reason PI-controller is best used with first-order processes (second-order closed loop system), and PID-controller with second-orded ones (third-order closed loop system). However, many processes have higher order than two, and still are controlled with PID-controllers. To tune it using pole placement techniques, it is necessary to consider only dominant poles, which affect performance of the system to the greatest extent. First, it is necessary to study a PI-controller with a second-order process, which is the most basic case. Tuning is performed using global optimization methods to fit dominant poles of a tuned system to dominant poles of a reference system.Розміщення полюсів замкненої системи гарантує отримання потрібних динамічних процесів. Кількість змінних параметрів регулятора визначає кількість полюсів, які з його використанням можливо розмістити. Значна кількість промислових процесів, які описані моделями порядку, вище другого, керуються ПІДрегуляторами. Через це потрібно використовувати методи розміщення домінантних полюсів замкненої системи. Це складно зробити аналітично, тому доцільно використовувати числову оптимізацію. Система автоматичного керування представлена об’єктом другого порядку з відомою передавальною функцією й регулятором із невідомими параметрами. Всього досліджено шість об’єктів як із ПІ-, так і з ПІД-регулятором. Для налаштування використано безумовну багатовимірну оптимізацію. Задачею оптимізації є мінімізації зваженої суми відстаней між відповідними полюсами налаштовуваної та бажаної систем. З використанням числових методів середовища Matlab було побудовано графіки цільової функції для ПІ-регулятора (поверхня) й ПІД-регулятора (набір ліній рівня, що заповнюють тривимірний простір). Налаштування системи з ПІД-регулятором у більшості випадків дозволяє точно відтворити задані полюси. Винятки становлять випадки з налаштування за парою комплексно-спряжених домінантних полюсів для випадку, коли недомінантний полюс було проігноровано. На противагу ПІД-регулятору, використання ПІ-регулятора накладає помітні обмеження на множину досяжних полюсів замкненої системи. Для будь-якого об’єкту існує нижня межа дійсної частини домінантних полюсів, тобто існує вертикальна пряма, ліворуч від якої полюси системи з ПІ-регулятором не можуть знаходитись. При досягненні цієї межі всі три полюси системи знаходяться на одній вертикальній прямій, тобто мають однакову дійсну частину. Порогове значення дійсної частини залежить від полюсів об’єкту. Наприклад, для аперіодичного об’єкту з кратним полюсом -0,4 ця межа має приблизне значення - 0,27, а для подібного коливального об’єкту з полюсами -0,4-0,2j і -0,4+0,2j ця межа близька до -0,8. Результат налаштування залежить від вагових коефіцієнтів у цільовій функції. Врахування недомінантного полюсу з таким самим ваговим коефіцієнтом, що й для домінантних полюсів, при налаштуванні ПІ-регулятора призводить до суттєвого погіршення результатів. Врахування недомінантного полюсу зі меншим ваговим коефіцієнтом може дати кращі результати, ніж налаштування лише за домінантними полюсами, а саме набір полюсів із тими самим дійсними частинами, але з меншими уявними. Графіки-поверхні цільової функції для ПІ-регулятора з будь-якого поєднання об’єкту, полюсів бажаної системи й вагових коефіцієнтів цільової функції на масштабах всього проміжку оптимізації мають подібний вигляд із глобальним мінімумом поблизу початку координат. На менших масштабах вигляд цих графіків може суттєво відрізнятися залежно від розташування полюсів об’єкту. Графіки можуть мати розриви, злами (лінії, на яких розрив має похідна цільової функції). Проте для аперіодичних і коливальних об’єктів, домінантні полюси яких мають однакові дійсні частини, цільова функція в близькому околі оптимуму має подібні за зовнішнім виглядом графіки попри те, що значення параметрів ПІ-регулятора помітно відрізняються. Візуалізація тривимірного поля значень цільової функції для систем із ПІД-регулятором показала так само показала схожі між собою результати на великих масштабах, але зі значними відмінностями в близькому околі оптимуму. Графіки для аперіодичних та коливальних об’єктів із однаковими дійсними частинами домінантних полюсів є подібними. Розглянутий метод налаштування регуляторів низького порядку дозволяє досягати розташування полюсів системи із заданим типом регулятора, яке є близьким до найкращого з усіх теоретично можливих

Reinforcement Learning: A Survey

This paper surveys the field of reinforcement learning from a computer-science perspective. It is written to be accessible to researchers familiar with machine learning. Both the historical basis of the field and a broad selection of current work are summarized. Reinforcement learning is the problem faced by an agent that learns behavior through trial-and-error interactions with a dynamic environment. The work described here has a resemblance to work in psychology, but differs considerably in the details and in the use of the word ``reinforcement.'' The paper discusses central issues of reinforcement learning, including trading off exploration and exploitation, establishing the foundations of the field via Markov decision theory, learning from delayed reinforcement, constructing empirical models to accelerate learning, making use of generalization and hierarchy, and coping with hidden state. It concludes with a survey of some implemented systems and an assessment of the practical utility of current methods for reinforcement learning.Comment: See http://www.jair.org/ for any accompanying file

A physics-based pi pre-layout tool for PCB PDN design

With increasingly stringent requirements for lower voltage supply, and higher density in PCB PDN design, now integrity (PI) is an increasingly important aspect that must be considered. A pre-layout tool based on the Cavity Model and Boundary Element Method is built to automatically achieve a specified target impedance for a multi-layered Printed Circuit Board (PCB) Power Distribution Network (PDN) design with a minimal number of decoupling capacitors. The pre-work about the post-layout design and analysis is proposed and the guidelines for creating a decoupling capacitors network with better performance has been built. With limit inputs, physical limitations for the minimal impedance that can be achieved in PDN system are calculated first to determine if a design is physically realizable and provide feedback to the user. The decoupling capacitor location will be determined by physics. Then a special decoupling capacitor selection algorithm through poles and zeros is utilized to determine which decoupling capacitor from a library should be added. Finally, the target impedance could be achieved using the minimum number of decoupling capacitors. Genetic algorithm is utilized to verify the performance and time cost of the new designed algorithm and several industry designs are used to verify the calculation result. The process is quite time-saving and convenient, and allows the user to do design discovery quickly, and determine the limiting factors under different conditions. --Abstract, page iii

Multivariable control of the space shuttle remote manipulator system using linearization by state feedback

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1993.Includes bibliographical references (p. 130-131).by Chang-Ching Lo Gettman.M.S

Technology Independent Synthesis of CMOS Operational Amplifiers

Analog circuit design does not enjoy as much automation as its digital counterpart. Analog sizing is inherently knowledge intensive and requires accurate modeling of the different parametric effects of the devices. Besides, the set of constraints in a typical analog design problem is large, involving complex tradeoffs. For these reasons, the task of modeling an analog design problem in a form viable for automation is much more tedious than the digital design. Consequently, analog blocks are still handcrafted intuitively and often become a bottleneck in the integrated circuit design, thereby increasing the time to market. In this work, we address the problem of automatically solving an analog circuit design problem. Specifically, we propose methods to automate the transistor-level sizing of OpAmps. Given the specifications and the netlist of the OpAmp, our methodology produces a design that has the accuracy of the BSIM models used for simulation and the advantage of a quick design time. The approach is based on generating an initial first-order design and then refining it. In principle, the refining approach is a simulated-annealing scheme that uses (i) localized simulations and (ii) convex optimization scheme (COS). The optimal set of input variables for localized simulations has been selected by using techniques from Design of Experiments (DOE). To formulate the design problem as a COS problem, we have used monomial circuit models that are fitted from simulation data. These models accurately predict the performance of the circuit in the proximity of the initial guess. The models can also be used to gain valuable insight into the behavior of the circuit and understand the interrelations between the different performance constraints. A software framework that implements this methodology has been coded in SKILL language of Cadence. The methodology can be applied to design different OpAmp topologies across different technologies. In other words, the framework is both technology independent and topology independent. In addition, we develop a scheme to empirically model the small signal parameters like \u27gm\u27 and \u27gds\u27 of CMOS transistors. The monomial device models are reusable for a given technology and can be used to formulate the OpAmp design problem as a COS problem. The efficacy of the framework has been demonstrated by automatically designing different OpAmp topologies across different technologies. We designed a two-stage OpAmp and a telescopic OpAmp in TSMC025 and AMI016 technologies. Our results show significant (10–15%) improvement in the performance of both the OpAmps in both the technologies. While the methodology has shown encouraging results in the sub-micrometer regime, the effectiveness of the tool has to be investigated in the deep-sub-micron technologies

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer EngineeringThe work presented in this thesis addresses the task of circuit optimization, helping the designer facing the high performance and high efficiency circuits demands of the market and technology evolution. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier. The main advantage of this new time-domain methodology is that, when a given settling-error is reached within the desired settling-time, it is automatically guaranteed that the amplifier has enough open-loop gain, AOL, output-swing (OS), slew-rate (SR), closed loop bandwidth and closed loop stability. Thus, this simplification of the circuit‟s evaluation helps the optimization process to converge faster. The method used to calculate the step response expression of the circuit is based on the inverse Laplace transform applied to the transfer function, symbolically, multiplied by 1/s (which represents the unity input step). Furthermore, may be applied to transfer functions of circuits with unlimited number of zeros/poles, without approximation in order to keep accuracy. Thus, complex circuit, with several design/optimization degrees of freedom can also be considered. The expression of the step response, from the proposed methodology, is based on the DC bias operating point of the devices of the circuit. For this, complex and accurate device models (e.g. BSIM3v3) are integrated. During the optimization process, the time-domain evaluation of the amplifier is used by the genetic algorithm, in the classification of the genetic individuals. The time-domain evaluator is integrated into the developed optimization platform, as independent library, coded using C programming language. The genetic algorithms have demonstrated to be a good approach for optimization since they are flexible and independent from the optimization-objective. Different levels of abstraction can be optimized either system level or circuit level. Optimization of any new block is basically carried-out by simply providing additional configuration files, e.g. chromosome format, in text format; and the circuit library where the fitness value of each individual of the genetic algorithm is computed. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. The communication by remote processing nodes is based on Message Passing interface (MPI). It is demonstrated that the distributed processing reduced the optimization run-time by more than one order of magnitude. Platform assessment is carried by several examples of two-stage amplifiers, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out and fabricated as a stand-alone circuit and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.Portuguese Foundation for the Science and Technology (FCT

Digital Pulse Width Modulator Techniques For Dc - Dc Converters

Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit