Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric. When penetration effects are neglected, the gate capacitance is independent of the dielectric material for a given equivalent oxide thickness (EOT). Our selfconsistent numerical results show that in the presence of wave function penetration, even for the same EOT, gate capacitance depends on the gate-dielectric material. Calculated gate capacitance is higher for materials with lower conduction band offsets with silicon. We have investigated the effects of substrate doping density on the relative error in gate capacitance due to neglecting wave function penetration. It is found that the error decreases with increasing doping density. We also show that accurate calculation of the gate capacitance including wave function penetration is not critically dependent on the value of the electron effective mass in the gate-dielectric region

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Grid infrastructures for the electronics domain: requirements and early prototypes from an EPSRC pilot project

The fundamental challenges facing future electronics design is to address the decreasing – atomistic - scale of transistor devices and to understand and predict the impact and statistical variability these have on design of circuits and systems. The EPSRC pilot project “Meeting the Design Challenges of nanoCMOS Electronics” (nanoCMOS) which began in October 2006 has been funded to explore this space. This paper outlines the key requirements that need to be addressed for Grid technology to support the various research strands in this domain, and shows early prototypes demonstrating how these requirements are being addressed

Disorder suppression and precise conductance quantization in constrictions of PbTe quantum wells

Conductance quantization was measured in submicron constrictions of PbTe, patterned into narrow,12 nm wide quantum wells deposited between Pb$_{0.92}$Eu$_{0.08}$Te barriers. Because the quantum confinement imposed by the barriers is much stronger than the lateral one, the one-dimensional electron energy level structure is very similar to that usually met in constrictions of AlGaAs/GaAs heterostructures. However, in contrast to any other system studied so far, we observe precise conductance quantization in $2e^2/h$ units, {\it despite of significant amount of charged defects in the vicinity of the constriction}. We show that such extraordinary results is a consequence of the paraelectric properties of PbTe, namely, the suppression of long-range tails of the Coulomb potentials due to the huge dielectric constant.Comment: 7 pages, 6 figures, submitted to Phys. Rev.

Avalanche noise characteristics of single Al/sub x/Ga/sub 1-x/As(0.3

Avalanche multiplication and excess noise have been measured on a series of Al/sub x/Ga/sub 1-x/As-GaAs and GaAs-Al/sub x/Ga/sub 1-x/As (x=0.3,0.45, and 0.6) single heterojunction p/sup +/-i-n/sup +/ diodes. In some devices excess noise is lower than in equivalent homojunction devices with avalanche regions composed of either of the constituent materials, the heterojunction with x=0.3 showing the greatest improvement. Excess noise deteriorates with higher values of x because of the associated increase in hole ionization in the Al/sub x/Ga/sub 1-x/As layer. It also depends critically upon the carrier injection conditions and Monte Carlo simulations show that this dependence results from the variation in the degree of noisy feedback processes on the position of the injected carriers

Monte Carlo study of current variability in UTB SOI DG MOSFETs

The scaling of conventional silicon based MOSFETs is increasingly difficult into the nanometer regime due to short channel effects, tunneling and subthreshold leakage current. Ultra-thin body silicon-on-insulator based architectures offer a promising alternative, alleviating these problems through their geometry. However, the transport behaviour in these devices is more complex, especially for silicon thicknesses below 10 nm, with enhancement from band splitting and volume inversion competing with scattering from phonons, Coulomb interactions, interface roughness and body thickness fluctuation. Here, the effect of the last scattering mechanism on the drive current is examined as it is considered a significant limitation to device performance for body thicknesses below 5 nm. A simulation technique that properly captures non-equilibrium transport, includes quantum effects and maintains computational efficiency is essential for the study of this scattering mechanism. Therefore, a 3D Monte Carlo simulator has been developed which includes this scattering effect in an ab initio fashion, and quantum corrections using the Density Gradient formalism. Monte Carlo simulations using `frozen field' approximation have been carried out to examine the dependence of mobility on silicon thickness in large, self averaging devices. This approximation is then used to carry out statistical studies of uniquely different devices to examine the variability of on-current. Finally, Monte Carlo simulations self consistent with Poisson's equation have been carried out to further investigate this mechanism

Magnetic biosensors: modelling and simulation

In the past few years, magnetoelectronics has emerged as a promising new platform technology in various biosensors for detection, identification, localisation and manipulation of a wide spectrum of biological, physical and chemical agents. The methods are based on the exposure of the magnetic field of a magnetically labelled biomolecule interacting with a complementary biomolecule bound to a magnetic field sensor. This Review presents various schemes of magnetic biosensor techniques from both simulation and modelling as well as analytical and numerical analysis points of view, and the performance variations under magnetic fields at steady and nonstationary states. This is followed by magnetic sensors modelling and simulations using advanced Multiphysics modelling software (e.g. Finite Element Method (FEM) etc.) and home-made developed tools. Furthermore, outlook and future directions of modelling and simulations of magnetic biosensors in different technologies and materials are critically discussed