A time-based approach for multi-GHz embedded mixed-signal characterization and measurement /

The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions.Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed

Experimental evaluation of sub-sampling IQ detection for low-level RF control in particle accelerator systems

The low-level radio frequency (LLRF) control system is one of the fundamental parts of a particle accelerator, ensuring the stability of the electro-magnetic (EM) field inside the resonant cavities. It leverages on the precise measurement of the field by in-phase/quadrature (IQ) detection of an RF probe signal from the cavities, usually performed using analogue downconversion. This approach requires a local oscillator (LO) and is subject to hardware non-idealities like mixer nonlinearity and long-term temperature drifts. In this work, we experimentally evaluate IQ detection by direct sampling for the LLRF system of the Polish free electron laser (PolFEL) now under development at the National Centre for Nuclear Research (NCBJ) in Poland. We study the impact of the sampling scheme and of the clock phase noise for a 1.3-GHz input sub-sampled by a 400-MSa/s analogue-to-digital converter (ADC), estimating amplitude and phase stability below 0.01% and nearly 0.01◦, respectively. The results are in line with state-of-the-art implementations, and demonstrate the feasibility of direct sampling for GHz-range LLRF systems

Jitter measurement built-in self-test circuit for phase locked loops

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 77-79).This paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal jitter resolution of 10 ps with a capture range of +/- 150 ps and does so in real time. The proposed application for this circuit is during manufacturing test of the PLL. The circuit is implemented in IBM's 90 nm process and was completed in the PLL and Clocking Development ASIC group at IBM Microelectronics in Essex Junction, Vermont as part of the VI-A program.by Brandon Ray Kam.M.Eng

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Theory and applications of delta-sigma analogue-to-digital converters without negative feedback

Analog-to-digital converters play a crucial role in modern audio and communication design. Conventional Nyquist converters are suitable only for medium resolutions and require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can achieve high resolutions (>20bits) and can be implemented using straightforward, high-tolerance analog components. In conventional oversampled modulators, negative feedback is applied in order to control the dynamic behavior of a system and to realize the attenuation of the quantization noise in the signal band due to noise shaping. However, feedback can also introduce undesirable effects such as limit cycles, jitter problems in continuous-time topologies, and infinite impulse responses. Additionally, it increases the system complexity due to extra circuit components such as nonlinear multi-bit digital-to-analog converters in the feedback path. Moreover, in certain applications such as wireless, biomedical sensory, or microphone implementations feedback cannot be applied. As a result, the main goal of this thesis is to develop sigma-delta data converters without feedback. Various new delta-sigma analog-to-digital converter topologies are explored their mathematical models are presented. Simulations are carried out to validate these models and to show performance results. Specifically, two topologies, a first-order and a second-order oscillator-based delta-sigma modulator without feedback are described in detail. They both can be implemented utilizing VCOs and standard digital gates, thus requiring only few components. As proof of concept, two digital microphones based on these delta-sigma converters without feedback were implemented and experimental results are given. These results show adequate performance and provide a new approach of measuring

Development of readout electronics for the ATLAS tile calorimeter at the HL-LHC

El Gran Colisionador de Hadrones (LHC) es uno de los experimentos más grandes en el mundo. El LHC ha sido diseñado para explorar las fronteras de la física, descubriendo el bosón de Higgs en el año 2012 a través de una colaboración compuesta por más de 7,000 científicos e ingenieros. Durante el año 2026 el acelerador LHC sufrirá una actualización que dará paso al nuevo acelerador High Luminosity LHC (HL-LHC). El nuevo acelerador aumentará la luminosidad instantánea en un factor 5 comparado con el actual LHC y hasta un factor 10 la lumninosidad integrada. El diseño del HL-LHC y la consecuente actualización de los experimentos instalados en él, representa un desafío tecnológico excepcional. Este nuevo acelerador conlleva el desarrollo de nuevas tecnologías de aceleradores como imanes superconductores y cavidades, así como sistemas electrónicos que permiten adquirir y procesar la extraordinaria cantidad de datos que se generarán. Esta tesis se desarrolla dentro del marco del proyecto Demonstrator. Este proyecto pretende la evaluación y cualificación del funcionamiento de la electrónica de adquisición para el HL-LHC antes de su instalación en el subdetector ATLAS Tile Calorimeter. El proyecto Demonstrator no sólo abarca programas de pruebas de la nueva electrónica con haces de partículas (testbeam), sino la instalación de un módulo Demonstrator dentro del detector ATLAS incluyendo nuevos desarrollos electrónicos llevados a cabo para el HL-LHC. El módulo Demonstrator ha sido probado en varias campañas de evaluación con haces de partículas. Este módulo consta de 4 estructuras mecánicas de aluminio (mini-drawers) donde cada una alberga 12 fotomultiplicadores, una tarjeta MainBoard y una tarjeta DaughterBoard cuya función es la de transmitir las señales digitalizadas de los PMTs al sistema de adquisición fuera del detector. En la parte más alejada del detector se encuentra el Tile PreProcessor (TilePPr), que es el primer y más importante componente del sistema de adquisición de datos del detector ATLAS Tile Calorimeter en el HL-LHC. Este prototipo integra dos FPGAs de alta generación para la procesado de datos recibidos del módulo "Demonstrator". Además, el TilePPr es responsable de la distribución del reloj en todo el detector, así como de transmitir los comandos de configuraci ón para seleccionar los diferentes modos de operación del módulo. La comunicación con el detector se realiza a través de cuatro módulos ópticos QSFP que proporcionan un ancho de banda de 160 Gbps. En esta tesis se presenta el diseño del primer prototipo TilePPr diseñado para la operación y lectura del módulo Demonstrator, así como los desarrollos firmware que se han realizado para la tarjeta DaughterBoard y TilePPr, en especial para los enlaces ópticos de alta velocidad. Además esta tarjeta se ha utilizado durante tres campañas de pruebas con haces de partículas donde se ha demonstrado su correcto funcionamiento como sistema de adquisición y como sistema para la distribución del reloj. Este documento se estructura en siete capítulos. El primer capítulo introduce el detector Tile Calorimeter y el sistema de selección de eventos actualmente utilizado en el ATLAS. Especialmente se centra en el principio de operación del detector, ya que no cambiará en el HL-LHC. El segundo capítulo introduce al HL-LHC así como a las actualizaciones necesarias en el experimento ATLAS para poder cumplir con los nuevos requerimientos. También se detalla los desarrollos electrónicos para el HL-LHC dentro del marco del proyecto Demonstrator, describiendo, por tanto, los detalles técnicos de los sistemas de electrónica de front-end y back-end. El tercer capítulo trata el diseño de la tarjeta TilePPr. Presenta los requerimientos y elementos fundamentales que la componen. Se incluyen también los detalles del proceso de diseño, desde la concepción de la tarjeta hasta los detalles físicos de la misma, acompañados de simulaciones de integridad de la señal y pruebas de verificación realizadas sobre el prototipo final. En el cuarto capítulo se abarca una descripción de los módulos firmware, tanto para el front-end como para el back-end, necesarios para la operación del módulo Demonstrator. En este capítulo se pone un énfasis especial en el desarrollo de los enlaces de alta velocidad, así como los aspectos que se han tenido en cuenta durante su diseño para que proporcionen una latencia fija y determinista. En un quinto capítulo se detalla el desarrollo de herramientas digitales implementadas en FPGA para la monitorización de diferencias de fase entre relojes. Este capítulo detalla las técnicas de undersampling utilizadas actualmente para la medida de diferencias de fases, y se propone un nuevo circuito basado en técnicas de undersampling que mejoran las capacidades del original. Además se muestran los resultados experimentales obtenidos y se explica las aplicaciones e implementación del circuito propuesto en el TilePPr para la sincronización del módulo con el reloj del LHC y monitorización de diferencias de fase. El capítulo sexto, introduce a las pruebas realizadas con haces de hadrones donde se puede ver el conjunto de la electrónica del front-end y back-end. Además se muestran análisis de los datos obtenidos que permite la comparación entre la electrónica actual y la diseñada para el HL-LHC. Finalmente se incluyen las conclusiones de esta tesis, así como el trabajo futuro vinculado a la continuación de la línea de investigación presentada.The Large Hadron Collider (LHC) is one of largest particle accelerators in the world. It has been used to explore energy frontier physics since 2010, with a collaboration composed of more than 7,000 scientists from 60 different countries. After a major upgrade that will occur in the 2020s, the LHC will become the High Luminosity LHC (HL-LHC). The HL-LHC will increase the instantaneous luminosity by a factor 5 compared to the LHC. The integrated luminosity of the HL-LHC program will be 10 times the integrated luminosity of LHC. The R&D HL-LHC efforts involve a large community in Europe, but also in the US and Japan. The design of the HL-LHC and the consequent upgrade of the experiments at the HL-LHC represents an exceptional technological challenge. New accelerator technologies are under development such as superconducting magnets and cavities and high-throughput electronics to receive and process the extraordinary amount of data generated by the experiments. In addition, the new readout and trigger architecture planned for the ATLAS in the HL-LHC requires a complete redesign of the front-end and back-end electronics systems to cope with the new requirements in radiation levels, data bandwidth and clocking distribution. This thesis is focused on the development of readout electronics for the ATLAS experiment at the HL-LHC, particularly in the design of the Tile Preprocessor (TilePPr) prototype envisaged for the readout of the Tile Calorimeter and communication with the ATLAS trigger system. Chapters 1 and 2 present an introduction to the LHC and HL-LHC experiments, followed by an extensive review of the Tile Calorimeter and the plans for the ATLAS Phase II Upgrade for the HL-LHC. The TilePPr prototype hardware design is fully described in Chapter 3, followed by the result of signal integrity simulations that confirmed the correct design of the PCB. At the end of the chapter some experimental results obtained during the initial tests with the first prototypes are presented. Chapter 4 describes all the firmware developments implemented for the operation of the Demonstrator module in the TilePPr prototype and in the DaughterBoard. This chapter includes a detailed description of all the firmware blocks designed for the front-end and back-end electronics, focusing in the development of high-speed data links with fixed and deterministic latency. Chapter 5 presents the development of FPGA-based circuits for the precise measurement of phase differences between clocks. A phase measurement circuit, called OSUS, based on oversampling techniques is discussed. The experimental results with the OSUS circuit obtained from its implementation in the TilePPr prototype are presented here. The OSUS circuit permits the synchronization of the Demonstrator module and the LHC clock, as well as the monitoring of the phase stability of clocks with a precision of about 30 psRMS. Chapter 6 includes a description of the testbeam setup and some experimental physics results obtained. During these testbeam campaigns the TilePPr prototype was the main readout system in the back-end electronics operating the Demonstrator module. Finally, the conclusions and future plans for this work are given at the end of this document

Instrumentation for parallel magnetic resonance imaging

Parallel magnetic resonance (MR) imaging may be used to increase either the throughput or the speed of the MR imaging experiment. As such, parallel imaging may be accomplished either through a "parallelization" of the MR experiment, or by the use of arrays of sensors. In parallelization, multiple MR scanners (or multiple sensors) are used to collect images from different samples simultaneously. This allows for an increase in the throughput, not the inherent speed, of the MR experiment. Parallel imaging with arrays of sensor coils, on the other hand, makes use of the spatial localization properties of the sensors in an imaging array to allow a reduction in the number of phase encodes required in acquiring an image. This reduced phase-encoding requirement permits an increase in the overall imaging speed by a factor up to the number of sensors in the imaging array. The focus of this dissertation has been the development of cost-effective instrumentation that would enable advances in the state of the art of parallel MR imaging. First, a low-cost desktop MR scanner was developed (< $13,000) for imaging small samples (2.54 cm fields-of view) at low magnetic field strengths (< 0.25 T). The performance of the prototype was verified through bench-top measurements and phantom imaging. The prototype transceiver has demonstrated an SNR (signal-to-noise ratio) comparable to that of a commercial MR system. This scanner could make parallelization of the MR experiment a practical reality, at least in the areas of small animal research and education. A 64-channel receiver for parallel MR imaging with arrays of sensors was also developed. The receiver prototype was characterized through both bench-top tests and phantom imaging. The parallel receiver is capable of simultaneous reception of up to sixty-four, 1 MHz bandwidth MR signals, at imaging frequencies from 63 to 200 MHz, with an SNR performance (on each channel) comparable to that of a single-channel commercial MR receiver. The prototype should enable investigation into the speed increases obtainable from imaging with large arrays of sensors and has already been used to develop a new parallel imaging technique known as single echo acquisition (SEA) imaging

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Undersampling bandpass modulator architectures

Continuous-time delta sigma modulators -- Undersampling Delta-sigma modulators for radio receivers -- A novel continuous-time delta sigma modulator -- New delta modulator based on undersampling