Contribución al modelado y diseño de moduladores sigma-delta en tiempo continuo de baja relación de sobremuestreo y bajo consumo de potencia

Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-µm CMOS technology and it has a measured peak SNR of 62.5dB

Stability of sinusoidal responses of marginally stable bandpass sigma delta modulators

In this paper, we analyze the stability of the sinusoidal responses of second order interpolative marginally stable bandpass sigma delta modulators (SDMs) with the sum of the numerator and denominator polynomials equal to one and explore new results on the more general second order interpolative marginally stable bandpass SDMs. These results can be further extended to the high order interpolative marginally stable bandpass SDMs

A describing function study of saturated quantization and its application to the stability analysis of multi-bit sigma delta modulators

Just as their single-bit counterparts, multi-bit sigma delta modulators exhibit nonlinear behavior due to the presence of the quantizer in the loop. In the multi-bit case this is caused by the fact that any quantizer has a limited output range and hence gives an implicit saturation effect. Due to this, any multi-bit modulator is prone to modulator overloading. Unfortunately, until now, designers had to rely on extensive time-domain simulations to predict the overloading level, because there is no adequate analytical theory to model this effect. In this work, we have developed such an analytical theory based on multiple input describing function analysis. This way, we obtained expressions for the signal gain, the noise gain and the variance of the quantization noise. Here, both the case of DC as well as sinusoidal signals was considered. These results were used for the stability analysis of multi-bit Sigma Delta modulators, which allows to predict the overloading level. Code implementing the proposed expressions is available for download at http://cas1.elis.ugent. be/cas/en/download

Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators

In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators. A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer coefficients but also exhibited greater robustness to non-idealties. Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work. In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator. This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio

Limit cycles in embedded high-order, lowpass sigma-delta modulators with distinct NTF zeros

In a related work by the authors, high-order sigma-delta (/spl Sigma//spl Delta/) modulators with distinct noise transfer function (NTF) zeros are decomposed into second-order and first-order subsystems, whose state-trajectories are then investigated by continuous-time embedding. This paper, based on the properties of these subsystems, furthers the study by introducing a scalable numerical method to locate the fixed-points on the generalized Poincare sections. A closed-form tangent linear manifold matrix for an arbitrary order modulator is derived, enabling the stability determination of the fixed-points and the accompanying limit cycles. Numerical examples show that the estimated DC input bound based on the boundary transition flow assumption cannot be relied on for modulators of order greater than fourlpublished_or_final_versio

High-loop-delay sixth-order bandpass continuous-time sigma-delta modulators

International audienceThis study focuses on the design of high-loop-delay modulators for parallel sigma-delta conversion. Parallel converters, allowing a global low oversampling ratio, consist of several bandpass modulators with adjacent central frequencies. To ensure the global performance, the noise transfer function (NTF) of each modulator must be adjusted regarding its central frequency. In this thematic a new topology of sixth-order modulators based on weighted-feedforward techniques is developed. This topology offers an adequate control of the NTF at each central frequency by simple means. Additive signal paths are moreover proposed to obtain an auto-filtering signal transfer function. An optimisation method is also developed to calculate the optimised coefficients of the modulators at different central frequencies. The main concerns are improving the stability and reducing the sensitivity of the continuous-time circuit to analogue imperfections. This is essential for parallel conversion since, in each channel, the modulator works at a central frequency which differs from the fourth of the sampling frequency. The performance of the optimised modulator is compared with its discrete-time counterpart with good argument

Global stability, limit cycles and chaotic behaviors of second order interpolative sigma delta modulators

It is well known that second order lowpass interpolative sigma delta modulators (SDMs) may suffer from instability and limit cycle problems when the magnitudes of the input signals are at large and at intermediate levels, respectively. In order to solve these problems, we propose to replace the second order lowpass interpolative SDMs to a specific class of second order bandpass interpolative SDMs with the natural frequencies of the loop filters very close to zero. The global stability property of this class of second order bandpass interpolative SDMs is characterized and some interesting phenomena are discussed. Besides, conditions for the occurrence of limit cycle and fractal behaviors are also derived, so that these unwanted behaviors will not happen or can be avoided. Moreover, it is found that these bandpass SDMs may exhibit irregular and conical-like chaotic patterns on the phase plane. By utilizing these chaotic behaviors, these bandpass SDMs can achieve higher signal-to-noise ratio (SNR) and tonal suppression than those of the original lowpass SDMs

Accurate stability prediction of 1-bit higher-order Δ-Σ modulators for multiple-sinusoidal inputs

The present approaches on predicting stability of Delta-Sigma (Δ-Σ) modulators are mostly confined to DC inputs. This poses limitations as practical applications of Δ-Σ modulators involve a wide range of signals other than DC such as multiple sinusoidal inputs for speech modeling. In this paper, a quasi-linear model for Δ-Σ modulators with nonlinear feedback control analysis is presented that accurately predicts stability of single-loop 1-bit higher-order Δ-Σ modulators for multiple sinusoids. Theoretical values are shown to match closely with simulation results. The results of this paper would enable optimization of the design of higher-order single-loop Δ-Σ modulators with increased dynamic ranges for various applications that require multiple-sinusoidal inputs or any general input composed of a finite number of sinusoidal components

Design of interpolative sigma delta modulators via a semi- infinite programming approach

This paper considers the design of interpolative sigma delta modulators (SDMs). The design problem is formulated as two different optimization problems. The first optimization problem is to determine the denominator coefficients. The objective of the optimization problem is to minimize the energy of the error function in the passband of the loop filter in which the error function reflects the noise output transfer function and the ripple of the input output transfer function. The constraint of the optimization problem refers to the specification of the error function defined in the frequency domain. The second optimization problem is to determine the numerator coefficients in which the cost function is to minimize the stopband ripple energy of the loop filter subject to the stability condition of the noise output and input output transfer functions. These two optimization problems are actually quadratic semi-infinite programming (SIP) problems. By employing our recently proposed dual parameterization method for solving the problems, global optimal solutions that satisfy the corresponding continuous constraint are guaranteed if the solutions exist. The advantages of this formulation are the guarantee of the stability of the noise output and input output transfer functions, applicability to design rational IIR filters without imposing specific filter structures such as Laguerre filter and Butterworth filter structures, and the avoidance of the iterative design of numerator and the denominator coefficients because the convergence of the iterative design is not guaranteed. Our simulation results show that this proposed design yields a significant improvement in the signal-to-noise ratio (SNR) compared to the existing designs