핀펫 소자에서의 핫캐리어 신뢰성 분석

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 신형철.CMOS 로직 소자는 퍼포먼스를 향상시키기 위해 지속적으로 축소화 되고 있다. 하지만 구조 파라미터들의 축소화에 비해 동작 전압은 충분히 감소하지 않는다. 따라서 소자 내 수직 전계나 온도가 증가하는 추세이기 때문에 신뢰성은 계속해서 문제가 되고 있다. 최근 3D 소자의 신뢰성에 대한 연구는 많이 진행되고 있지만 empirical 모델링과 관련된 연구가 대부분이다. 따라서 본 연구에서는 실제 측정을 기반으로 시뮬레이션을 이용하여 물리적 이론 중심으로 로직 소자의 핫캐리어 신뢰성을 분석하였다. 먼저 핫캐리어 모델의 정확성을 향상시키기 위해서 TCAD 시뮬레이션에 electron-electron scattering을 적용하였다. 추가적으로 3D FinFET의 측정 데이터와 calibration을 진행하여 모델의 정합성을 확인하였다. calibration 과정에서는 모든 scattering 메커니즘을 고려하기 위해 다양한 전압과 온도 조건이 필요하다. 따라서 다양한 전압 조건에 따른 HCD를 분석하고, calibration을 진행하여 HCD 모델의 파라미터를 추출하였다. 다음으로 전압 조건에 따른 HCD의 온도 경향성을 분석하였다. oxide trap과 달리 interface trap은 전압 조건에 따라 다른 온도 경향성을 보인다. 따라서 interface trap을 3가지 성분으로 분리하여 각 성분의 온도 경향성을 분석하였다. Multiple particle process(MP)과 field enhanced thermal degradation process(FP)는 전압 조건과 상관없이 일정한 온도 경향성을 가진다. 반면 Single particle process(SP)는 scattering의 영향을 받기 때문에 온도 경향성은 전압 조건에 따라 달라진다. 온도 경향성 분석 과정에서도 calibration을 진행하며 여러 번의 iteration을 통해 다양한 전압 및 온도가 고려된 파라미터를 추출한다. 추출된 파라미터를 적용한 시뮬레이션 모델은 기존의 모델보다 더 정확하게 HCD 측정 결과를 예측하였다. 결과적으로 물리적 이론에 근거하여 시뮬레이션 모델 구축함으로써 HCD 분석의 정확성을 향상시켰다. 하지만 가속 조건과 동작 조건의 self-heating 효과가 다르기 때문에 소자가 실제 CMOS 회로의 동작 조건에서 interface trap을 발생시키는 메커니즘은 다를 수 있다. 따라서 우리는 동작 영역에서의 각 성분의 비율까지 예측하였다. 마지막으로 우리는 10 nm node 소자에서 nFinFET에 비해 pFinFET에서 높은 열화가 발생하는 원인에 대해 분석하였다. pFinFET은 소스/드레인 물질로 SiGe를 사용하기 때문에 nFinFET에 비해 self-heating 효과가 심하여 소자 온도가 도 높다. 이론적으로 MP 메커니즘의 lifetime은 온도가 증가할수록 감소하기 때문에 MP에 의한 열화 또한 감소한다. 따라서 소자 온도가 더 높은 pFinFET에서 nFinFET에 비해 더 많은 MP가 발생하기 어렵다. 하지만 nFinFET 과 달리 pFinFET에서는 Si-H bond의 electron과 hole이 반응하여 interface trap을 생성시키는 RD 가 발생할 수 있다. 또한 RD는 온도가 높을수록 더 많은 열화가 발생하기 때문에, pFinFET에서 nFinFET보다 더 많은 열화가 발생하는 현상을 설명할 수 있다. 따라서 우리는 HCD 조건이지만 소자 온도가 높은 pFinFET에서 추가적인 RD 메커니즘이 발생할 수 있다고 제안한다. 다양한 전압 조건에서의 전류 열화율을 통해 주요 열화 메커니즘을 분석하였으며 pFinFET에서는 RD가 주요함을 확인하였다. 또한 TCAD 시뮬레이션을 이용하여 HCD 조건에서 발생할 수 있는 RD를 예측하였다. 그 결과 RD를 제외한 순수 hot carrier 성분은 pFinFET보다 nFinFET에서 더 많이 발생한다.CMOS logic devices have been scaled down to improve performance. However, the operating voltage is not sufficiently reduced compared to the scale down in physical dimensions. Therefore, since the electric field and temperature of the device gradually increase, reliability is still a critical issue in logic devices. Recently, many studies on the reliability of 3D devices are being conducted, but most of the studies are related to empirical modeling. Therefore, in this study, based on the actual measurement results, the hot carrier degradation(HCD) reliability of the logic device was analyzed focusing on the physical theory using Technology computer-aided design (TCAD) simulation. First, electron-electron scattering(EES) was applied to the TCAD simulation to improve the accuracy of the hot carrier model. Additionally, calibration between the measurement data of 14 nm node FinFET and the model was performed to confirm the consistency. The calibration process required various voltage and temperature conditions to account for all scattering mechanisms. Therefore, HCD was analyzed according to various voltage conditions, and the parameters of the HCD model were extracted by calibration process. Next, temperature dependence under various HCD conditions was analyzed. Unlike oxide traps, interface traps show different temperature dependence depending on HCD voltage conditions. Therefore, the interface traps were separated into three components and the temperature dependence was analyzed for each component. Multiple particle process (MP) and Field enhanced thermal degradation process (FP) have a constant temperature dependence regardless of voltage conditions. On the other hand, the temperature dependence of Single particle process (SP) varies depending on the voltage condition because SP is affected by scattering. In the process of temperature dependence analysis, calibration is also performed and parameters considering various voltages and temperatures were extracted through several iterations. The improved model to which the extracted parameters were applied showed more precise prediction of degradation compared to that of the previous model. As a results, accuracy of the HCD analysis was improved by establishing the HCD simulation framework based on physical theories. However, since the self-heating effect of the acceleration condition and the operation condition are different, the HCD mechanism that occurs in the actual CMOS circuit may also be different. Therefore, we predicted the ratio of each component under operating condition. Finally, in 10 nm node devices, we analyzed the cause of higher HCD in pFinFETs than in nFinFETs. Self-heating effect is severe in pFinFETs because SiGe is used as the source/drain material which makes the device temperature higher than nFinFETs. Theoretically, because the lifetime of multiple particle(MP) mechanism decreases as temperature increases, degradation due to MP decreases. Therefore, it is difficult for the HCD mechanisms to occur more in pFinFETs which has higher temperature than nFinFETs. However, in pFinFETs unlike nFinFETs, reaction-diffusion (RD) mechanism can occur in which holes react with the electrons of Si-H bonds to generate interface traps. Also, since RD deteriorates more as the temperature increases, the phenomenon that more degradation occurs in pFinFET than nFinFET can be explained by the RD mechanism. Therefore, we propose an additional RD mechanism that is caused by high device temperature in pFinFETs even in HCD condition. Main components were investigated through measurements of current degradation rate in various voltage conditions, and it was found that RD is dominant in pFinFETs. Also, RD that can occur in HCD condition was predicted through TCAD simulation. As a results, degradation due to pure hot carriers without RD occurs more in nFinFETs than in pFinFETs.Abstract i Chapter 1. Introduction 1 Chapter 2. Hot Carrier Degradation Model 4 2.1. Physical theory 4 2.2. TCAD simulation 8 2.3. Calibration process 14 2.4. Summary 22 Chapter 3. Analysis on Temperature Dependence of HCD 25 3.1. Introduction 25 3.2. Temperature dependence according to acceleration conditions 26 3.3. Calibration process 30 3.4. Mechanism separation 33 3.5. HCD prediction in the nominal voltage 35 3.6. Summary 36 Chapter 4. Comparative Analysis of HCD in nMOS/pMOS FinFET 39 4.1. Introduction 39 4.2. Comparison of HCD in the long/short channel FinFET 40 4.3. Self-heating effect in n/pFinFET 44 4.4. Bias Temperature Instability(BTI) in n/pFinFET 47 4.5. Summary 59 Chapter 5. Conclusion 64 Abstract in Korean 66 List of Publications 69Docto

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Modeling the Interdependences between Voltage Fluctuation and BTI Aging

With technology scaling, the susceptibility of circuits to different reliability degradations is steadily increasing. Aging in transistors due to bias temperature instability (BTI) and voltage fluctuation in the power delivery network of circuits due to IR-drops are the most prominent. In this paper, we are reporting for the first time that there are interdependences between voltage fluctuation and BTI aging that are nonnegligible. Modeling and investigating the joint impact of voltage fluctuation and BTI aging on the delay of circuits, while remaining compatible with the existing standard design flow, is indispensable in order to answer the vital question, “what is an efficient (i.e., small, yet sufficient) timing guardband to sustain the reliability of circuit for the projected lifetime?” This is, concisely, the key goal of this paper. Achieving that would not be possible without employing a physics-based BTI model that precisely describes the underlying generation and recovery mechanisms of defects under arbitrary stress waveforms. For this purpose, our model is validated against varied semiconductor measurements covering a wide range of voltage, temperature, frequency, and duty cycle conditions. To bring reliability awareness to existing EDA tool flows, we create standard cell libraries that contain the delay information of cells under the joint impact of aging and IR-drop. Our libraries can be directly deployed within the standard design flow because they are compatible with existing commercial tools (e.g., Synopsys and Cadence). Hence, designers can leverage the mature algorithms of these tools to accurately estimate the required timing guardbands for any circuit despite its complexity. Our investigation demonstrates that considering aging and IR-drop effects independently, as done in the state of the art, leads to employing insufficient and thus unreliable guardbands because of the nonnegligible (on average 15% and up to 25%) underestimations. Importantly, considering interdependences between aging and IR-drop does not only allow correct guardband estimations, but it also results in employing more efficient guardbands

적층 나노시트 구조의 음의 정전용량 전계 효과 트랜지스터

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 최우영.The development of integrated circuit (IC) technology has continued to improve speed and capacity through miniaturization of devices. However, power density is increasing rapidly due to the increasing leakage current as miniaturization advances. Although the remarkable advancement of process technology has allowed complementary-metal-oxide-semiconductor (CMOS) technology to consistently overcome its constraints, the physical limitations of the metal-oxide-semiconductor field-effect transistor (MOSFET) are unmanageable. Accordingly, research on logic device is being divided into a CMOS-extension and a beyond-CMOS. CMOS-extension focuses on the gate-all-around field-effect transistors (GAAFETs) which is a promising architecture for future CMOS thanks to the excellent electrostatic gate controllability. Particularly, nanosheet (NS) architecture with high current drivability required in ICs, is the most promising. However, NS GAAFET has a trade-off relation between the controllability and the drivability, which requires the necessity of a higher-level effective oxide thickness (EOT) scaling for further scaling of NS GAAFET. On the other hand, beyond-CMOS mainly focuses on developing devices with novel mechanisms to overcome the MOSFETs' physical limits. Among several candidates, negative capacitance field-effect transistors (NCFETs) with exceptional CMOS compatibility and current drivability are highlighted as future logic devices for low-power, high-performance operation. Although the NCFET utilizing the negative capacitance (NC) effect of a ferroelectric has been demonstrated theoretically by the Landau model, it is challenging to be implemented due to the fact that stabilized NC and sub-thermionic subthreshold swing (SS) are incompatible. In this dissertation, a GAA NCFET that maintains a stable capacitance boosting by NC effect and exhibits high performance is demonstrated. A ferroelectric-antiferroelectric mixed-phase hafnium-zirconium-oxide (HZO) thin film was introduced, whose effect was confirmed by capacitors and FET experiments. Furthermore, the mixed-phase HZO was demonstrated on a stacked nanosheet gate-all-around (stacked NS GAA) structure, the advanced CMOS technology, which exhibits a superior gate controllability as well as a satisfactory drivability for ICs. The hysteresis-free stable NC operation with the superior performance was confirmed in NS GAA NCFET. The improved SS and on-current (Ion) compared to MOSFETs fabricated in the same manner were validated, and its feasibility as a low-power, high-performance logic device was proven based on a variety of figure of merits.집적회로 기술의 발전은 소자의 소형화를 통한 속도 및 용량의 향상을 위해 발전을 거듭해왔다. 그러나 소형화를 거듭할수록 증가하는 누설전류의 문제로 전력 밀도가 급격하게 증가하고 있다. 상보형 금속-산화막-반도체(CMOS) 기술은 눈부신 공정기술의 성장에 힘입어 한계를 끊임없이 극복해왔으나, 기존의 금속-산화막-반도체 전계-효과-트랜지스터(MOSFET)의 물리적 한계는 극복할 수 없는 문제이다. 이에 따라 논리 반도체에 관한 연구는 CMOS를 연장하는 방향과 CMOS를 뛰어넘는 방향으로 나뉘어 진행되고 있다. CMOS를 연장하는 방향은 뛰어난 정전기적 게이트 장악력을 갖는 차세대 CMOS 구조로 유망한 게이트-올-어라운드 전계-효과-트랜지스터(GAAFET)에 관한 연구가 주를 이룬다. 특히 높은 전류 구동력을 가질 수 있는 나노시트(NS) 구조가 가장 유망한데, 게이트 장악력이 전류 구동력과 상충된다는 단점이 있다. 이에 따라 NS GAAFET 기술을 위해서는 더 높은 수준의 유효산화막두께 (EOT) 스케일링이 필수적이다. 한편, CMOS를 뛰어넘는 방향의 연구는 MOSFET의 물리적 한계를 극복하기 위해 새로운 메커니즘을 갖는 소자를 개발하는 방향으로 이루어진다. 다양한 후보군 중 CMOS 호환성과 전류 구동능력이 뛰어난 음의 정전용량 전계-효과-트랜지스터(NCFET)이 저전력, 고성능 동작을 위한 미래 CMOS 소자로 각광받고 있다. 강유전체의 음의 정전용량 (NC) 효과를 이용한 NCFET은 Landau 모델에 의해 이론적으로 증명되었으나, 열역학적으로 안정한 상태와 60 mV/dec 이하의 문턱전압-이하-기울기(SS)를 동시에 구현하기 불가능하다는 문제가 있다. 본 학위논문에서는 안정한 정전용량 향상 특성을 가지며 높은 성능을 갖는 NS GAA NCFET을 구현하였다. 강유전체(ferroelectric)-반강유전체(antiferroelectric) 혼합상(mixed-phase) 하프늄-지르코늄-옥사이드(HZO) 박막의 정전용량 향상 효과를 커패시터 및 FET 제작을 통해 효과를 검증하였다. 또한 높은 게이트 장악력을 가지며 집적회로에서 요구하는 전류 구동력을 만족시킬 수 있는 적층형 나노시트 게이트-올-어라운드(stacked NS GAA) 구조에 혼합상 NC 박막을 적용한 FET을 시연하고 성능의 우수성을 확인하였다. 동일하게 제작된 MOSFET 대비 향상된 SS와 구동 전류(Ion)를 확인하였고, 다양한 성능 지수를 토대로 저전력, 고성능 로직 소자로서의 타당성을 검증하였다.Abstract i Contents iv List of Table vii List of Figures viii Chapter 1 Introduction 1 1.1 Power and Area Scaling Challenges 1 1.2 Nanosheet Gate-All-Around FETs 5 1.2.1 Gate-All-Around FETs 5 1.2.2 Nanosheet GAAFETs 6 1.3 Negative Capacitance FETs 11 1.3.1 Negative Capacitance in Ferroelectric Materials 11 1.3.2 Negative Capacitance for Steep Switching Devices 14 1.3.3 Stable NC vs. Sub-thermionic SS 17 1.4 Scope and Organization of Dissertation 21 Chapter 2 Stacked NS GAA NCFET with Ferroelectric-Antiferroelectric-Mixed-Phase HZO 22 2.1 Mixed-Phase HZO for Capacitance Boosting 22 2.2 NS GAA NCFET using Mixed-Phase HZO 25 Chapter 3 HZO ALD Stack Optimization 28 3.1 Metal-Ferroelectric-Interlayer-Silicon (MFIS) / MFM Capacitors 29 3.1.1 Fabrication of MFIS Capacitors 29 3.1.2 Electrical Characteristics of MFIS / MFM Capacitors 33 3.2 SOI Planar NCFETs 38 3.2.1 DC Measurements 38 3.2.2 Direct Capacitance Measurements 47 3.2.3 Speed Measurements 49 Chapter 4 Device Fabrication of Stacked NS GAA NCFET 51 4.1 Initial Process Flow of NS GAA NCFET 52 4.2 Process Issues and Solution 56 4.2.1 External Resistance 56 4.2.2 TiN Gate Sidewall Spacer 60 4.2.3 Unintentionally Etched Sacrificial Layer 65 4.2.4 Discussions 68 4.3 Channel Release Process 69 4.3.1 Consideration in Channel Release Process 69 4.3.2 Methods for SiGe Selective Etching 72 4.3.3 SiGe Selective Etching using Carboxylic Acid Solution 75 4.4 Revised Process of NS GAA NCFET 78 Chapter 5 Electrical Characteristics of Fabricated NS GAA NCFET 84 5.1 DC Characteristics 85 5.1.1 NS GAA NCFET vs. Planar SOI NCFET 85 5.1.2 Performance Enhancement of NS GAA NCFET 88 5.1.3 Performance Evaluation 96 5.2 Operating Temperature Properties 99 Chapter 6 Conclusion 102 Bibliography 105 초 록 115박

Electrical Characterisation of III-V Nanowire MOSFETs

The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to theoxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits

Study of High-k Dielectrics and their Interfaces on Semiconductors for Device Applications

This thesis has focused on two emerging applications of high-k dielectrics in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and in Metal-InsulatorSemiconductor High Electron Mobility Transistors (MIS-HEMTs). The key aim has been to propose the best routes for passivation of semiconductor/high-k oxide interfaces by investigating the band alignments and interface properties of several oxides, such as Tm2O3, Ta2O5, ZrO2, Al2O3 and MgO, deposited on different semiconductors: Si, Ge, GaN, InGaAs and InGaSb. The electrical characterisation of fabricated MIS capacitor and (MIS)-HEMT devices have also been performed. Thulium silicate (TmSiO) has been identified as a promising candidate for integration as interfacial layer (IL) in HfO2/TiN MOSFETs. The physical properties of Tm2O3/IL/Si interface have been elucidated, where IL (TmSiO) has been formed using different post-deposition annealing (PDA) temperatures, from 550 to 750 °C. It has been found that the best-scaled stack (sub-nm IL) is formed at 550 °C PDA with a graded interface layer and a strong SiOx (Si 3+) component. A large valence band offset (VBO) of 2.8 eV and a large conduction band offset (CBO) of 1.9 eV have been derived for Tm2O3/Si by X-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry. Further increase of device performance can be achieved by replacing Si with GaN for high frequency, high power and high-temperature operation. In this thesis, several GaN cleaning procedures have been considered: 30% NH4OH, 20% (NH4)2S, and 37% HCl. It has been found that the HCl treatment shows the lowest oxygen contamination and Garich surface, and hence has been used prior sputtering of Ta2O5, Al2O3, ZrO2 and MgO on GaN. The large VBOs of 1.1 eV and 1.2 eV have been derived for Al2O3 and MgO on GaN respectively, using XPS and Kraut’s method; the corresponding CBOs are 2.0 eV and 2.8 eV respectively, taking into account the band gaps of Al2O3 (6.5 eV) and MgO (7.4 eV) determined from XPS O 1s electron energy spectra. The lowest leakage currents were obtained for devices with Al2O3 and MgO, i.e. 5.3 ×10-6 A/cm2 and 3.2 ×10-6 A/cm2 at 1 V, respectively in agreement with high band offsets (> 1 eV). Furthermore, the effect of different surface treatments (HCl, O2 plasma and 1-Octadecanethiol (ODT)) prior to atomic layer deposition of Al2O3 on the GaN/AlGaN/GaN heterostructure has been investigated. The MIS-HEMTs fabricated using the low-cost ODT GaN surface treatment have been found to exhibit superior performance for power switching applications such as a low threshold voltage, VT of -12.3 V, hysteresis of 0.12 V, a small subthreshold voltage slope (SS) of 73 mV/dec, and a low density of interface states, Dit of 3.0 x10^12 cm-2eV-1. A comprehensive novel study of HfO2/InGaAs and Al2O3/InGaSb interfaces have also been conducted for use in III-V based MOSFETs. The addition of the plasma H2/TMA/H2 pre-cleaning has been found to be very effective in recovering etch damage on InGaAs, especially for (110) orientation, and led to the improvement of electrical characteristics. Furthermore, the combination of H2 plasma exposure and forming gas anneal yielded significantly improved metrics for Al2O3/InGaSb over the control HCltreated sample, with the 150 W plasma treatment giving both the highest capacitance and the lowest stretch out

Nanoscale Field Emission Devices for High-Temperature and High-Frequency Operation

Field emission—the quantum-mechanical tunneling of electrons from the surface of a material into vacuum by means of a strong electric field—has been studied for over a century. However, the usage of devices based on this mechanism has been limited to a handful of niche applications such as high-power RF systems and field emission displays. The preference for solid-state devices relies on their low cost, long lifetimes, reduced power consumption, ease of integrability, and simple and scalable fabrication. Nonetheless, with the advent of modern fabrication techniques, it has been possible to build field emission devices with nanoscale dimensions that offer several advantages over traditional semiconductor devices. The use of vacuum allows ballistic transport with no lattice scattering. As device capacitance can be engineered by tuning the geometry, these devices are appealing for high-frequency operation. Vacuum is also inherently immune to harsh operating conditions such as high temperature and radiation, which is desirable for aerospace, nuclear, and military applications. In addition, even though field emission requires substantial electric fields, by exploiting the nanoscale gaps that can be easily fabricated with state-of-the-art lithographic capabilities, we can expect operating voltages comparable to CMOS. Thus, vacuum emission devices have the potential to greatly improve upon the limitations of current technologies. In this work, we experimentally demonstrate various design paradigms to develop nanoscale field emission devices for high-temperature environments and high-frequency operation. First, we propose suspended lateral two- and four-terminal devices. By removing the underlying solid substrate, we aim to increase the resistance of the leakage current pathways that emerge at elevated temperatures. Tungsten is the chosen electrode material due to its low work function and ability to withstand high temperatures. Our next architecture consists of a multi-tip two-terminal array, which exclusively relies on the inherent fast response of field emission. Due to the strong non-linearity in the emission characteristic, frequency mixing is measured. Lastly, we combine field emission with plasmonics to conceive devices that can be modulated both electrically and optically at telecommunication wavelength. By taking advantage of the strong confinement and significant optical field enhancement of surface plasmon polaritons, we seek to minimize the applied voltages required for field emission as well as the necessary laser powers for photoemission towards the development of high-speed, low-power, nanoscale optoelectronic systems.</p