Improved Fault Tolerant SRAM Cell Design & Layout in 130nm Technology

Technology scaling of CMOS devices has made the integrated circuits vulnerable to single event radiation effects. Scaling of CMOS Static RAM (SRAM) has led to denser packing architectures by reducing the size and spacing of diffusion nodes. However, this trend has led to the increase in charge collection and sharing effects between devices during an ion strike, making the circuit even more vulnerable to a specific single event effect called the single event multiple-node upset (SEMU). In nanometer technologies, SEMU can easily disrupt the data stored in the memory and can be more hazardous than a single event single-node upset. During the last decade, most of the research efforts were mainly focused on improving the single event single-node upset tolerance of SRAM cells by using novel circuit techniques, but recent studies relating to angular radiation sensitivity has revealed the importance of SEMU and Multi Bit Upset (MBU) tolerance for SRAM cells. The research focuses on improving SEMU tolerance of CMOS SRAM cells by using novel circuit and layout level techniques. A novel SRAM cell circuit & layout technique is proposed to improve the SEMU tolerance of 6T SRAM cells with decreasing feature size, making it an ideal candidate for future technologies. The layout is based on strategically positioning diffusion nodes in such a way as to provide charge cancellation among nodes during SEMU radiation strikes, instead of charge build-up. The new design & layout technique can improve the SEMU tolerance levels by up to 20 times without sacrificing on area overhead and hence is suitable for high density SRAM designs in commercial applications. Finally, laser testing of SRAM based configuration memory of a Xilinx Virtex-5 FPGA is performed to analyze the behavior of SRAM based systems towards radiation strikes

AXTAR: Mission Design Concept

The Advanced X-ray Timing Array (AXTAR) is a mission concept for X-ray timing of compact objects that combines very large collecting area, broadband spectral coverage, high time resolution, highly flexible scheduling, and an ability to respond promptly to time-critical targets of opportunity. It is optimized for submillisecond timing of bright Galactic X-ray sources in order to study phenomena at the natural time scales of neutron star surfaces and black hole event horizons, thus probing the physics of ultradense matter, strongly curved spacetimes, and intense magnetic fields. AXTAR's main instrument, the Large Area Timing Array (LATA) is a collimated instrument with 2-50 keV coverage and over 3 square meters effective area. The LATA is made up of an array of supermodules that house 2-mm thick silicon pixel detectors. AXTAR will provide a significant improvement in effective area (a factor of 7 at 4 keV and a factor of 36 at 30 keV) over the RXTE PCA. AXTAR will also carry a sensitive Sky Monitor (SM) that acts as a trigger for pointed observations of X-ray transients in addition to providing high duty cycle monitoring of the X-ray sky. We review the science goals and technical concept for AXTAR and present results from a preliminary mission design study.Comment: 19 pages, 10 figures, to be published in Space Telescopes and Instrumentation 2010: Ultraviolet to Gamma Ray, Proceedings of SPIE Volume 773

Performance monitor counters: Interplay between safety and security in complex cyber-physical systems

Recent years have witnessed the growth of the adoption of cyber-physical systems (CPSs) in many sectors, such as automotive, aerospace, civil infrastructures, and healthcare. Several CPS applications include critical scenarios, where a failure of the system can lead to catastrophic consequences. Therefore, anomalies due to failures or malicious attacks must be detected timely. This paper focuses on two relevant aspects of the design of a CPS: 1) safety and 2) security. It analyzes in a specific scenario how the performance monitor counters (PMCs) available in several commercial microprocessors can be from the one hand a valuable tool to enhance the safety of a system and, on the other hand, a security backdoor. Starting from the example of a PMC-based safety mechanism, this paper shows the implementation of a possible attack and eventually proposes a strategy to mitigate the effectiveness of the attack while preserving the safety of the system

A Static Analyzer for Large Safety-Critical Software

We show that abstract interpretation-based static program analysis can be made efficient and precise enough to formally verify a class of properties for a family of large programs with few or no false alarms. This is achieved by refinement of a general purpose static analyzer and later adaptation to particular programs of the family by the end-user through parametrization. This is applied to the proof of soundness of data manipulation operations at the machine level for periodic synchronous safety critical embedded software. The main novelties are the design principle of static analyzers by refinement and adaptation through parametrization, the symbolic manipulation of expressions to improve the precision of abstract transfer functions, the octagon, ellipsoid, and decision tree abstract domains, all with sound handling of rounding errors in floating point computations, widening strategies (with thresholds, delayed) and the automatic determination of the parameters (parametrized packing)

Verifying Recursive Active Documents with Positive Data Tree Rewriting

This paper proposes a data tree-rewriting framework for modeling evolving documents. The framework is close to Guarded Active XML, a platform used for handling XML repositories evolving through web services. We focus on automatic verification of properties of evolving documents that can contain data from an infinite domain. We establish the boundaries of decidability, and show that verification of a {\em positive} fragment that can handle recursive service calls is decidable. We also consider bounded model-checking in our data tree-rewriting framework and show that it is \nexptime-complete

INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements