Enhancing Digital Controllability in Wideband RF Transceiver Front-Ends for FTTx Applications

Enhancing the digital controllability of wideband RF transceiver front-ends helps in widening the range of operating conditions and applications in which such systems can be employed. Technology limitations and design challenges often constrain the extensive adoption of digital controllability in RF front-ends. This work focuses on three major aspects associated with the design and implementation of a digitally controllable RF transceiver front-end for enhanced digital control. Firstly, the influence of the choice of semiconductor technology for a system-on-chip integration of digital gain control circuits are investigated. The digital control of gain is achieved by utilizing step attenuators that consist of cascaded switched attenuation stages. A design methodology is presented to evaluate the influence of the chosen technology on the performance of the three conventionally used switched attenuator topologies for desired attenuation levels, and the constraints that the technology suitable for high amplification places on the attenuator performance are examined. Secondly, a novel approach to the integrated implementation of gain slope equalization is presented, and the suitability of the proposed approach for integration within the RF front-end is verified. Thirdly, a sensitivity-aware implementation of a peak power detector is presented. The increased employment of digital gain control also increases the requirements on the sensitivity of the power detector employed for adaptive power and gain control. The design, implementation, and measurement results of a state-of-the-art wideband power detector with high sensitivity and large dynamic range are presented. The design is optimized to provide a large offset cancellation range, and the influence of offset cancellation circuits on the sensitivity of the power detector is studied. Moreover, design considerations for high sensitivity performance of the power detector are investigated, and the noise contributions from individual sub-circuits are evaluated. Finally, a wideband RF transceiver front-end is realized using a commercially available SiGe BiCMOS technology to demonstrate the enhancements in the digital controllability of the system. The RF front-end has a bandwidth of 500 MHz to 2.5 GHz, an input dynamic range of 20 dB, a digital gain control range larger than 30 dB, a digital gain slope equalization range from 1.49 dB/GHz to 3.78 dB/GHz, and employs a power detector with a sensitivity of -56 dBm and dynamic range of 64 dB. The digital control in the RF front-end is implemented using an on-chip serial-parallel-interface (SPI) that is controlled by an external micro-controller. A prototype implementation of the RF front-end system is presented as part of an RFIC intended for use in optical transceiver modules for fiber-to-the-x applications

High gain and bandwidth current-mode amplifiers : study and implementation

Doutoramento em Engenharia ElectrotécnicaEsta tese aborda o problema do projecto de amplificadores com grandes produtos de ganho por largura de banda. A aplicação final considerada consistiu no projecto de amplificadores adequados à recepção de sinais ópticos em sistemas de transmissão ópticos usando o espaço livre. Neste tipo de sistemas as maiores limitações de ganho e largura de banda surgem nos circuitos de entrada. O uso de detectores ópticos com grande área fotosensível é uma necessidade comum neste tipo de sistemas. Estes detectores apresentam grandes capacidades intrínsecas, o que em conjunto com a impedância de entrada apresentada pelo amplificador estabelece sérias restrições no produto do ganho pela largura de banda. As técnicas mais tradicionais para combater este problema recorrem ao uso de amplificadores com retroacção baseados em configurações de transimpedância. Estes amplificadores apresentam baixas impedâncias de entrada devido à acção da retroacção. Contudo, os amplificadores de transimpedância também apresentam uma relação directa entre o ganho e a impedância de entrada. Logo, diminuir a impedância de entrada implica diminuir o ganho. Esta tese propõe duas técnicas novas para combater os problemas referidos. A primeira técnica tem por base uma propriedade fundamental dos amplificadores com retroacção. Em geral, todos os circuitos electrónicos têm tempos de atraso associados, os amplificadores com retroacção não são uma excepção a esta regra. Os tempos de atraso são em geral reconhecidos como elementos instabilizadores neste tipos da amplificadores. Contudo, se usados judiciosamente, este tempos de atraso podem ser explorados como uma forma da aumentar a largura de banda em amplificadores com retroacção. Com base nestas ideias, esta tese apresenta o conceito geral de reatroacção com atraso, como um método de optimização de largura de banda em amplificadores com retroacção. O segundo método baseia-se na destruição da dualidade entre ganho e impedância de entrada existente nos amplificadores de transimpedância. O conceito de adaptação activa em modo de corrente é neste sentido uma forma adequada para separar o detector óptico da entrada do amplificador. De acordo com este conceito, emprega-se um elemento de adaptação em modo de corrente para isolar o detector óptico da entrada do amplificador. Desta forma as tradicionais limitações de ganho e largura de banda podem ser tratadas em separado. Esta tese defende o uso destas técnicas no desenho de amplificadores de transimpedância para sistemas de recepção de sinais ópticos em espaço livre.This thesis addresses the problem of achieving high gain-bandwidth products in amplifiers. The adopted framework consisted on the design of a free-space optical (FSO) front end amplifier able to amplify very small optical signals over large frequency bandwidths. The major gain-bandwidth limitations in FSO front end amplifiers arise due to the input circuitry. Usually, it is necessary to have large area optical detectors in order to maximize signal reception. These detectors have large intrinsic capacitances, which together with the amplifier input impedance poses a severe restriction on the gain-bandwidth product. Traditional techniques to combat this gain-bandwidth limitation resort to feedback amplifiers consisting on transimpedance configurations. These amplifiers have small input impedances due to the feedback action. Nevertheless, transimpedance amplifiers have a direct relation between gain and input impedance. Thus reducing the input impedance usually implies reducing the gain. This thesis advances two new methods suitable to combat the above mentioned problems. The first method is based on a fundamental property of feedback amplifiers. In general, all electronic circuits have associated time delays, and feedback amplifiers are not an exception to this rule. Time delays in feedback amplifiers have been recognized as destabilizing elements. Nevertheless, when used with appropriate care, these delays can be exploited as bandwidth enhancement elements. Based on these ideas, this thesis presents the general concept of delayed feedback, as a bandwidth optimization method suitable for feedback amplifiers. The second method is based on the idea of destroying the impedance-gain duality in transimpedance amplifiers. The concept of active current matching is in this sense a suitable method to detach the optical detector from the transimpedance amplifier input. According to this concept, a current matching device (CMD) is used to convey the signal current sensed by the optical detector, to the amplifier’s input. Using this concept the traditional gainbandwidth limitations can be treated in a separate fashion. This thesis advocates the usage of these techniques for the design of transimpedance amplifiers suited for FSO receiving systems

Techniques for signal to noise ratio adaptation in infared optical wireless for optimisation of receiver performance

The challenge of creating a new environment of links for wireless infrared and optical local area networks (LANs) is driving new innovations in the design of optical transceivers. This thesis is concerned with a systematic approach to the design of receivers for indoor optical wireless communication. In particular, it is concerned with how to offer bandwidth adjustment capability in a receiver according to the dynamic service quality of the incoming signals. Another part of the discussion of the thesis is how one can properly choose the front-end preamplifier and biasing circuitry for the photodetector. Also, comparison is made between different types of amplifier, and the methods of bandwidth enhancement. The designs of six different techniques of integrating transimpedance amplifiers, with photodetectors to adapt an adjustable bandwidth control receiver are discussed. The proposed topologies provide an adjustable range of bandwidths for different frequency ranges, typically between 52Hz to 115MHz. The composite technique designs were used to incorporate into a system with an automatic gain control to study its effect, on an optical wireless receiver which had bandwidth adjustment and automatic gain adjustment. Theoretical analysis of noise performance for all the designed circuits is also presented. The theory and design of obstacles of indoor optical wireless receiver delivery, in addition to techniques for mitigating these effects, are discussed. This shows that infrared is a viable alternative to ratio for certain applications

Realization of Integrable Low- Voltage Companding Filters for Portable System Applications

Undoubtedly, today’s integrated electronic systems owe their remarkable performance primarily to the rapid advancements of digital technology since 1970s. The various important advantages of digital circuits are: its abstraction from the physical details of the actual circuit implementation, its comparative insensitiveness to variations in the manufacturing process, and the operating conditions besides allowing functional complexity that would not be possible using analog technology. As a result, digital circuits usually offer a more robust behaviour than their analog counterparts, though often with area, power and speed drawbacks. Due to these and other benefits, analog functionality has increasingly been replaced by digital implementations. In spite of the advantages discussed above, analog components are far from obsolete and continue to be key components of modern electronic systems. There is a definite trend toward persistent and ubiquitous use of analog electronic circuits in day-to-day life. Portable electronic gadgets, wireless communications and the widespread application of RF tags are just a few examples of contemporary developments. While all of these electronic systems are based on digital circuitry, they heavily rely on analog components as interfaces to the real world. In fact, many modern designs combine powerful digital systems and complementary analog components on a single chip for cost and reliability reasons. Unfortunately, the design of such systems-on-chip (SOC) suffers from the vastly different design styles of analog and digital components. While mature synthesis tools are readily available for digital designs, there is hardly any such support for analog designers apart from wellestablished PSPICE-like circuit simulators. Consequently, though the analog part usually occupies only a small fraction of the entire die area of an SOC, but its design often constitutes a major bottleneck within the entire development process. Integrated continuous-time active filters are the class of continuous-time or analog circuits which are used in various applications like channel selection in radios, anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a filter is the dynamic range; this is the ratio of the largest to the smallest signal that can be applied at the input of the filter while maintaining certain specified performance. The dynamic range required in the filter varies with the application and is decided by the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the capacitor area of an integrated active filter increases in proportion to its dynamic range. This situation is incompatible with the needs of integrated systems, especially battery operated ones. In addition to this fundamental dependence of power dissipation on dynamic range, the design of integrated active filters is further complicated by the reduction of supply voltage of integrated circuits imposed by the scaling down of technologies to attain twin objective of higher speed and lower power consumption in digital circuits. The reduction in power consumption with decreasing supply voltage does not apply to analog circuits. In fact, considerable innovation is required with a reduced supply voltage even to avoid increasing power consumption for a given signal to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer. A technique which has attracted the attention of circuit designers as a possible route to filters with higher dynamic range per unit power consumption is “companding”. Companding (compression-expansion) filters are a very promising subclass of continuous-time analog filters, where the input (linear) signal is initially compressed before it will be handled by the core (non-linear) system. In order to preserve the linear operation of the whole system, the non-linear signal produced by the core system is converted back to a linear output signal by employing an appropriate output stage. The required compression and expansion operations are performed by employing bipolar transistors in active region or MOS transistors in weak inversion; the systems thus derived are known as logarithmic-domain (logdomain) systems. In case MOS transistors operated in saturation region are employed, the derived structures are known as Square-root domain systems. Finally, the third class of companding filters can also be obtained by employing bipolar transistors in active region or MOS transistors in weak inversion; the derived systems are known as Sinh-domain systems. During the last several years, a significant research effort has been already carried out in the area of companding circuits. This is due to the fact that their main advantages are the capability for operation in low-voltage environment and large dynamic range originated from their companding nature, electronic tunability of the frequency characteristics, absence of resistors and the potential for operations in varied frequency regions.Thus, it is obvious that companding filters can be employed for implementing high-performance analog signal processing in diverse frequency ranges. For example, companding filters could be used for realizing subsystems in: xDSL modems, disk drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked loops, FM stereo demodulator, touch-tone telephone tone decoder and crossover network used in a three-way high-fidelity loudspeaker etc. A number of design methods for companding filters and their building blocks have been introduced in the literature. Most of the proposed filter structures operate either above 1.5V or under symmetrical (1.5V) power supplies. According to data that provides information about the near future of semiconductor technology, International Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of analog integrated circuits is the usage of low-voltage building blocks that use a single 0.5-1.5V power supply. Therefore, the present investigation was primarily concerned with the study and design of low voltage and low power Companding filters. The work includes the study about: the building blocks required in implementing low voltage and low power Companding filters; the techniques used to realize low voltage and low power Companding filters and their various areas of application. Various novel low voltage and low power Companding filter designs have been developed and studied for their characteristics to be applied in a particular portable area of application. The developed designs include the N-th order universal Companding filter designs, which have been reported first time in the open literature. Further, an endeavor has been made to design Companding filters with orthogonal tuning of performance parameters so that the designs can be simultaneously used for various features. The salient features of each of the developed circuit are described. Electronic tunability is one of the major features of all of the designs. Use of grounded capacitors and resistorless designs in all the cases makes the designs suitable for IC technology. All the designs operate in a low-voltage and low-power environment essential for portable system applications. Unless specified otherwise, all the investigations on these designs are based on the PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The performance of each circuit has been validated by comparing the characteristics obtained using simulation with the results present in the open literature. The proposed designs could not be realized in silicon due to non-availability of foundry facility at the place of study. An effort has already been started to realize some of the designs in silicon and check their applicability in practical circuits. At the basic level, one of the proposed Companding filter designs was implemented using the commercially available transistor array ICs (LM3046N) and was found to verify the theoretical predictions obtained from the simulation results

An Optoelectronic Stimulator for Retinal Prosthesis

Retinal prostheses require the presence of viable population of cells in the inner retina. Evaluations of retina with Age-Related Macular Degeneration (AMD) and Retinitis Pigmentosa (RP) have shown a large number of cells remain in the inner retina compared with the outer retina. Therefore, vision loss caused by AMD and RP is potentially treatable with retinal prostheses. Photostimulation based retinal prostheses have shown many advantages compared with retinal implants. In contrary to electrode based stimulation, light does not require mechanical contact. Therefore, the system can be completely external and not does have the power and degradation problems of implanted devices. In addition, the stimulating point is flexible and does not require a prior decision on the stimulation location. Furthermore, a beam of light can be projected on tissue with both temporal and spatial precision. This thesis aims at fi nding a feasible solution to such a system. Firstly, a prototype of an optoelectronic stimulator was proposed and implemented by using the Xilinx Virtex-4 FPGA evaluation board. The platform was used to demonstrate the possibility of photostimulation of the photosensitized neurons. Meanwhile, with the aim of developing a portable retinal prosthesis, a system on chip (SoC) architecture was proposed and a wide tuning range sinusoidal voltage-controlled oscillator (VCO) which is the pivotal component of the system was designed. The VCO is based on a new designed Complementary Metal Oxide Semiconductor (CMOS) Operational Transconductance Ampli er (OTA) which achieves a good linearity over a wide tuning range. Both the OTA and the VCO were fabricated in the AMS 0.35 µm CMOS process. Finally a 9X9 CMOS image sensor with spiking pixels was designed. Each pixel acts as an independent oscillator whose frequency is controlled by the incident light intensity. The sensor was fabricated in the AMS 0.35 µm CMOS Opto Process. Experimental validation and measured results are provided

A high performance ASIC for electrical and neurochemical traumatic brain injury monitoring

Traumatic Brain Injury (TBI) can be defined as a non-degenerative, non-congenital brain trauma due to an external mechanical force. TBI is a major cause of death and disability in all age groups and the leading cause of death and disability in working people and among young adults. This Thesis presents the first application specific integrated chip (ASIC) for monitoring patients suffering from TBI. The microelectronic chip was designed to meet the demands of processing physiological signals for an alternative method of TBI monitoring. It has been studied that by monitoring electrical (ECoG) and chemical (glucose, lactate and potassium) signals, the report of spreading depolarisation (SD) waves could be a good indicator for an upcoming secondary brain injury. The ultimate aim of this Thesis has been to support the idea of a “behind-the-ear” micro-platform, which could enable the monitoring of mobile (or mobilized) patients suffering a TBI who, currently, are not monitored. Switched-capacitor (SC) circuits have been adopted for the implementation of both current and voltage analogue front-ends (AFEs). Advanced techniques to minimise noise and improve the noise performance of the circuit were employed. Moreover, a digitally enabled automatic transimpedance gain control circuit, suitable for current analogue front-ends, was developed and tested in order to provide an automated way to adjust the gain and to counterbalance for the drop in sensitivity of the biosensors due to drift. Measured results confirming the operation of the TBI ASIC and its sub-circuits are reported. Finally, a novel circuit that mimics the Butler-Volmer dynamics is presented. The basic building blocks arise from the combination of Translinear (TL) Circuits and the Non- linear Bernoulli Cell Formalism (NBCF). The developed electrical equivalent circuit has been compared to an ideal model, which was developed in MATLAB. The robustness of the microelectronic system was evaluated by means of Monte Carlo simulations.Open Acces

Collective analog bioelectronic computation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 677-710).In this thesis, I present two examples of fast-and-highly-parallel analog computation inspired by architectures in biology. The first example, an RF cochlea, maps the partial differential equations that describe fluid-membrane-hair-cell wave propagation in the biological cochlea to an equivalent inductor-capacitor-transistor integrated circuit. It allows ultra-broadband spectrum analysis of RF signals to be performed in a rapid low-power fashion, thus enabling applications for universal or software radio. The second example exploits detailed similarities between the equations that describe chemical-reaction dynamics and the equations that describe subthreshold current flow in transistors to create fast-and-highly-parallel integrated-circuit models of protein-protein and gene-protein networks inside a cell. Due to a natural mapping between the Poisson statistics of molecular flows in a chemical reaction and Poisson statistics of electronic current flow in a transistor, stochastic effects are automatically incorporated into the circuit architecture, allowing highly computationally intensive stochastic simulations of large-scale biochemical reaction networks to be performed rapidly. I show that the exponentially tapered transmission-line architecture of the mammalian cochlea performs constant-fractional-bandwidth spectrum analysis with O(N) expenditure of both analysis time and hardware, where N is the number of analyzed frequency bins. This is the best known performance of any spectrum-analysis architecture, including the constant-resolution Fast Fourier Transform (FFT), which scales as O(N logN), or a constant-fractional-bandwidth filterbank, which scales as O (N2).(cont.) The RF cochlea uses this bio-inspired architecture to perform real-time, on-chip spectrum analysis at radio frequencies. I demonstrate two cochlea chips, implemented in standard 0.13m CMOS technology, that decompose the RF spectrum from 600MHz to 8GHz into 50 log-spaced channels, consume < 300mW of power, and possess 70dB of dynamic range. The real-time spectrum analysis capabilities of my chips make them uniquely suitable for ultra-broadband universal or software radio receivers of the future. I show that the protein-protein and gene-protein chips that I have built are particularly suitable for simulation, parameter discovery and sensitivity analysis of interaction networks in cell biology, such as signaling, metabolic, and gene regulation pathways. Importantly, the chips carry out massively parallel computations, resulting in simulation times that are independent of model complexity, i.e., O(1). They also automatically model stochastic effects, which are of importance in many biological systems, but are numerically stiff and simulate slowly on digital computers. Currently, non-fundamental data-acquisition limitations show that my proof-of-concept chips simulate small-scale biochemical reaction networks at least 100 times faster than modern desktop machines. It should be possible to get 103 to 106 simulation speedups of genome-scale and organ-scale intracellular and extracellular biochemical reaction networks with improved versions of my chips. Such chips could be important both as analysis tools in systems biology and design tools in synthetic biology.by Soumyajit Mandal.Ph.D

Integrated analog focal plane processing for automatic alignment

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (p. 161-168).by Christopher Bruce Umminger.Ph.D