10 research outputs found
A review on reversible logic gates
In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.
Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic
A Library-Based Synthesis Methodology for Reversible Logic
In this paper, a library-based synthesis methodology for reversible circuits
is proposed where a reversible specification is considered as a permutation
comprising a set of cycles. To this end, a pre-synthesis optimization step is
introduced to construct a reversible specification from an irreversible
function. In addition, a cycle-based representation model is presented to be
used as an intermediate format in the proposed synthesis methodology. The
selected intermediate format serves as a focal point for all potential
representation models. In order to synthesize a given function, a library
containing seven building blocks is used where each building block is a cycle
of length less than 6. To synthesize large cycles, we also propose a
decomposition algorithm which produces all possible minimal and inequivalent
factorizations for a given cycle of length greater than 5. All decompositions
contain the maximum number of disjoint cycles. The generated decompositions are
used in conjunction with a novel cycle assignment algorithm which is proposed
based on the graph matching problem to select the best possible cycle pairs.
Then, each pair is synthesized by using the available components of the
library. The decomposition algorithm together with the cycle assignment method
are considered as a binding method which selects a building block from the
library for each cycle. Finally, a post-synthesis optimization step is
introduced to optimize the synthesis results in terms of different costs.Comment: 24 pages, 8 figures, Microelectronics Journal, Elsevie
Design and synthesis of reversible logic
Energy lost during computation is an important issue for digital design. Today, all electronics devices suffer from energy lost due to the conventional logic system used. The amount of energy loss in the form of heat leads to immense challenges in nowadays circuit design. To overcome that, reversible logic has been invented. Since properties of reversible logic differ greatly than conventional logic, synthesis methods used for conventional logic cannot be used in reversible logic. In this dissertation, we proposed new synthesis algorithms and several circuit designs using reversible logic
Synthesis, testing and tolerance in reversible logic
In recent years, reversible computing has established itself as a promising research area and emerging technology. This thesis focuses on three important areas of reversible logic, which is an area of reversible computing. Firstly, this thesis proposes a transformation based synthesis approach for realizing conservative reversible functions using SWAP and Fredkin gates. This thesis also proposes ten templates for optimizing SWAP and Fredkin gates-based reversible circuits. Secondly, this thesis proposes an approach for the design of online testable reversible circuits. A reversible circuit composed of NOT, CNOT and Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. Finally, we have proposed an approach to achieve fault tolerance in reversible circuits. A design of a 3-bit reversible majority voter circuit is presented. This voter circuit can be used to design fault tolerant reversible circuits
QUANTUM COMPUTING AND HPC TECHNIQUES FOR SOLVING MICRORHEOLOGY AND DIMENSIONALITY REDUCTION PROBLEMS
Tesis doctoral en período de exposición públicaDoctorado en Informática (RD99/11)(8908