Performance and resource modeling for FPGAs using high-level synthesis tools

High-performance computing with FPGAs is gaining momentum with the advent of sophisticated High-Level Synthesis (HLS) tools. The performance of a design is impacted by the input-output bandwidth, the code optimizations and the resource consumption, making the performance estimation a challenge. This paper proposes a performance model which extends the roofline model to take into account the resource consumption and the parameters used in the HLS tools. A strategy is developed which maximizes the performance and the resource utilization within the area of the FPGA. The model is used to optimize the design exploration of a class of window-based image processing application

Empowering parallel computing with field programmable gate arrays

After more than 30 years, reconfigurable computing has grown from a concept to a mature field of science and technology. The cornerstone of this evolution is the field programmable gate array, a building block enabling the configuration of a custom hardware architecture. The departure from static von Neumannlike architectures opens the way to eliminate the instruction overhead and to optimize the execution speed and power consumption. FPGAs now live in a growing ecosystem of development tools, enabling software programmers to map algorithms directly onto hardware. Applications abound in many directions, including data centers, IoT, AI, image processing and space exploration. The increasing success of FPGAs is largely due to an improved toolchain with solid high-level synthesis support as well as a better integration with processor and memory systems. On the other hand, long compile times and complex design exploration remain areas for improvement. In this paper we address the evolution of FPGAs towards advanced multi-functional accelerators, discuss different programming models and their HLS language implementations, as well as high-performance tuning of FPGAs integrated into a heterogeneous platform. We pinpoint fallacies and pitfalls, and identify opportunities for language enhancements and architectural refinements

Dynamic Power Evaluation of LTE Wireless Baseband Processing on FPGA

International audienceMobile networks and user equipments continuously evolve to circumvent the data traffic growth and the increasing number of users. However, the complexity and heterogeneity of such systems (3G, LTE, LTE-A, etc.) makes power one of the most critical metric. In this context, power estimation has become an unavoidable task in the design process. In this paper, a dynamic power estimation methodology for FPGA-based systems is presented. It aims at providing accurate and fast power estimations of an entire system prior to its implementation. It also aims at making design space exploration easier. We introduce an innovative scenario-level in order to facilitate the comparison of domain-specific systems. We show the effectiveness of our approach on several LTE baseband configurations which leads to a low absolute error, compared to classic estimations. It also exhibits a high speed-up factor which is determinant during design space exploration. I. INTRODUCTION Today, the data traffic that is generated on mobile networks continues to grow rapidly. According to [1], global mobile data increases of 69% in 2014 and it will have a compound annual growth rate of 57% from 2014 to 2019. To deal with these issues, mobile networks and user equipments tend to constantly adapt their processing capabilities. Among all possible solutions, a popular example is the LTE standard. The complexity of systems like LTE makes their design and development a challenging task, especially when they are implemented in embedded systems in which specific constraints have to be taken into account (power, size, performance , etc.). The number of parameters that can have an impact over power consumption makes the power estimation even more difficult. As the new technologies clearly enhance the performance in terms of throughput, QoS, it also implies a higher power consumption and more heat dissipation. One of the most popular families of digital circuits in embedded systems are the Field Programmable Gate Arrays (FPGA). These devices represent an attractive technology and make it possible to implement complex systems due to their high density of gates and heterogeneous resources. As compare to ASIC that can achieve better performance [2], FPGAs offer more flexibility. FPGA-based systems can be made of IP (Intellectual Property) which are hardware cores that facilitate design reuse and speed up development time. Their power consumption is generally divided into static and dynamic power. Static power comes from leakage currents whereas dynamic power is generated by the transistors switching activity as soon as the circuit is active

An FPGA implementation of OFDM transceiver for LTE applications

The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The transceiver is implemented on a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. The transmitter frame can be reconfigured for different pilot and data schemes. In the receiver, time-domain synchronization is achieved thr ough a joint maximum likelihood (ML) symbol arrival-time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). A least-squares channel estimation retrieves the channel state information and a simple zero-forcing scheme has been implemented for channel equalization. Results show that a rough implementation of the signal path can be impleme nted by using only Xilinx System Generator for DSP

The hArtes Tool Chain

This chapter describes the different design steps needed to go from legacy code to a transformed application that can be efficiently mapped on the hArtes platform

A Task-Graph Execution Manager for Reconfigurable Multi-tasking Systems

Reconfigurable hardware can be used to build multi tasking systems that dynamically adapt themselves to the requirements of the running applications. This is especially useful in embedded systems, since the available resources are very limited and the reconfigurable hardware can be reused for different applications. In these systems computations are frequently represented as task graphs that are executed taking into account their internal dependencies and the task schedule. The management of the task graph execution is critical for the system performance. In this regard, we have developed two dif erent versions, a software module and a hardware architecture, of a generic task-graph execution manager for reconfigurable multi-tasking systems. The second version reduces the run-time management overheads by almost two orders of magnitude. Hence it is especially suitable for systems with exigent timing constraints. Both versions include specific support to optimize the reconfiguration process

Embedded harmonic control for dynamic trajectory planning on

This paper presents a parallel hardware implementation of a well-known navigation control method on reconfigurable digital circuits. Trajectories are estimated after an iterated computation of the harmonic functions, given the goal and obstacle positions of the navigation problem. The proposed massively distributed implementation locally computes the direction to choose to get to the goal position at any point of the environment. Changes in this environment may be immediately taken into account, for example when obstacles are discovered during an on-line exploration. The implementation results show that the proposed architecture simultaneously improves speed, power consumption, precision, and environment size.