16 research outputs found
Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors
The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 ”W. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 ”m TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit
Circuits for Analog Signal Processing Employing Unconventional Active Elements
DisertaÄnĂ prĂĄce se zabĂœvĂĄ zavĂĄdÄnĂm novĂœch struktur modernĂch aktivnĂch prvkĆŻ pracujĂcĂch v napÄĆ„ovĂ©m, proudovĂ©m a smĂĆĄenĂ©m reĆŸimu. FunkÄnost a chovĂĄnĂ tÄchto prvkĆŻ byly ovÄĆeny prostĆednictvĂm SPICE simulacĂ. V tĂ©to prĂĄci je zahrnuta Ćada simulacĂ, kterĂ© dokazujĂ pĆesnost a dobrĂ© vlastnosti tÄchto prvkĆŻ, pĆiÄemĆŸ velkĂœ dĆŻraz byl kladen na to, aby tyto prvky byly schopny pracovat pĆi nĂzkĂ©m napĂĄjecĂm napÄtĂ, jelikoĆŸ poptĂĄvka po pĆenosnĂœch elektronickĂœch zaĆĂzenĂch a implantabilnĂch zdravotnickĂœch pĆĂstrojĂch stĂĄle roste. Tyto pĆĂstroje jsou napĂĄjeny bateriemi a k tomu, aby byla prodlouĆŸena jejich ĆŸivotnost, trend navrhovĂĄnĂ analogovĂœch obvodĆŻ smÄĆuje k stĂĄle vÄtĆĄĂmu sniĆŸovĂĄnĂ spotĆeby a napĂĄjecĂho napÄtĂ. HlavnĂm pĆĂnosem tĂ©to prĂĄce je nĂĄvrh novĂœch CMOS struktur: CCII (Current Conveyor Second Generation) na zĂĄkladÄ BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na zĂĄkladÄ FG, transkonduktor na zĂĄkladÄ novĂ© techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na zĂĄkladÄ GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na zĂĄkladÄ GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na zĂĄkladÄ BD. DĂĄle je uvedeno nÄkolik zajĂmavĂœch aplikacĂ uĆŸĂvajĂcĂch vĂœĆĄe jmenovanĂ© prvky. ZĂskanĂ© vĂœsledky simulacĂ odpovĂdajĂ teoretickĂœm pĆedpokladĆŻm.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.
Low Voltage Low Power Analogue Circuits Design
DisertaÄnĂ prĂĄce je zamÄĆena na vĂœzkum nejbÄĆŸnÄjĆĄĂch metod, kterĂ© se vyuĆŸĂvajĂ pĆi nĂĄvrhu analogovĂœch obvodĆŻ s vyuĆŸitĂ nĂzkonapÄĆ„ovĂœch (LV) a nĂzkopĆĂkonovĂœch (LP) struktur. Tyto LV LP obvody mohou bĂœt vytvoĆeny dĂky vyspÄlĂœm technologiĂm nebo takĂ© vyuĆŸitĂm pokroÄilĂœch technik nĂĄvrhu. DisertaÄnĂ prĂĄce se zabĂœvĂĄ prĂĄvÄ pokroÄilĂœmi technikami nĂĄvrhu, pĆedevĆĄĂm pak nekonvenÄnĂmi. Mezi tyto techniky patĆĂ vyuĆŸitĂ prvkĆŻ s ĆĂzenĂœm substrĂĄtem (bulk-driven - BD), s plovoucĂm hradlem (floating-gate - FG), s kvazi plovoucĂm hradlem (quasi-floating-gate - QFG), s ĆĂzenĂœm substrĂĄtem s plovoucĂm hradlem (bulk-driven floating-gate - BD-FG) a s ĆĂzenĂœm substrĂĄtem s kvazi plovoucĂm hradlem (quasi-floating-gate - BD-QFG). PrĂĄce je takĂ© orientovĂĄna na moĆŸnĂ© zpĆŻsoby implementace znĂĄmĂœch a modernĂch aktivnĂch prvkĆŻ pracujĂcĂch v napÄĆ„ovĂ©m, proudovĂ©m nebo mix-mĂłdu. Mezi tyto prvky lze zaÄlenit zesilovaÄe typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za ĂșÄelem potvrzenĂ funkÄnosti a chovĂĄnĂ vĂœĆĄe zmĂnÄnĂœch struktur a prvkĆŻ byly vytvoĆeny pĆĂklady aplikacĂ, kterĂ© simulujĂ usmÄrĆovacĂ a induktanÄnĂ vlastnosti diody, dĂĄle pak filtry dolnĂ propusti, pĂĄsmovĂ© propusti a takĂ© univerzĂĄlnĂ filtry. VĆĄechny aktivnĂ prvky a pĆĂklady aplikacĂ byly ovÄĆeny pomocĂ PSpice simulacĂ s vyuĆŸitĂm parametrĆŻ technologie 0,18 m TSMC CMOS. Pro ilustraci pĆesnĂ©ho a ĂșÄinnĂ©ho chovĂĄnĂ struktur je v disertaÄnĂ prĂĄci zahrnuto velkĂ© mnoĆŸstvĂ simulaÄnĂch vĂœsledkĆŻ.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the nonâconventional ones which are bulkâdriven (BD), floatingâgate (FG), quasiâfloatingâgate (QFG), bulkâdriven floatingâgate (BDâFG) and bulkâdriven quasiâfloatingâgate (BDâQFG) techniques. The thesis also looks at ways of implementing structures of wellâknown and modern active elements operating in voltageâ, currentâ, and mixedâmode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fullyâdifferential second generation current conveyor (FBâCCII), fullyâbalanced differential difference amplifier (FBâDDA), voltage differencing transconductance amplifier (VDTA), currentâcontrolled current differencing buffered amplifier (CCâCDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diodeâless rectifier and inductance simulations, as well as lowâpass, bandâpass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.
A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design
Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 ”W. PSpice simulation results using the 0.18 ”m CMOS technology from TSMC are included to verify the design functionality and correspondence with theory
CMOS current amplifiers : speed versus nonlinearity
This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered.
For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived that, unlike other reported macromodels, can accurately predict the common-mode behaviour in differential applications. Similarly, this model is used to describe the nonidealities of several other current-mode amplifiers because similar circuit structures are common in such amplifiers. With modern low-voltage CMOS-technologies, the current-mode operational amplifier and the high-gain current-conveyor (CCIIâ) perform better than open-loop current-amplifiers. Similarly, unlike with conventional voltage-mode operational amplifiers, the large-signal settling behaviour of these two amplifier types does not degrade as CMOS-processes are scaled down.
In this work, two 1 MHz 3rd -order low-pass continuous-time filters are realised with a 1.2 ÎŒm CMOS-process. These filters use a differential CCIIâ with linearised, dynamically biased output stages resulting in performance superior to most OTA-C filter realisations reported. Similarly, two logarithmic amplifier chips are designed and fabricated. The first circuit, implemented with a 1.2 ÎŒm BiCMOS-process, uses again a CCIIâ. This circuit uses a pn-junction as a logarithmic feedback element. With a CCIIâ the constant gain-bandwidth product, typical of voltage-mode operational amplifiers, is avoided resulting in a constant 1 MHz bandwidth with a 60 dB signal amplitude range. The second current-mode logarithmic amplifier, based on piece-wise linear approximation of the logarithmic function by a cascade of limiting current amplifier stages, is realised in a standard 1.2 ÎŒm CMOS-process. The limiting level in these current amplifiers is less sensitive to process variation than in limiting voltage amplifiers resulting in exceptionally low temperature dependency of the logarithmic output signal. Additionally, along with this logarithmic amplifier a new current peak detectoris developed.reviewe
Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques
Energy efficiency is a key requirement in the design of amplifiers for modern wireless
applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to
achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to
implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is
presented as a design example, including some of the techniques described. The amplifier has been
fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage,
ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and
large-signal performance.Agencia Estatal de InvestigaciĂłn PID2019-107258RB-C32UniĂłn Europea PID2019-107258RB-C3
Energy-efficient amplifiers based on quasi-floating gate techniques
Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32
New Possibilities In Low-voltage Analog Circuit Design Using Dtmos Transistors
(Doktora) -- Ä°stanbul Teknik Ăniversitesi, Fen Bilimleri EnstitĂŒsĂŒ, 2013(PhD) -- Ä°stanbul Technical University, Institute of Science and Technology, 2013Bu çalıĆmada DTMOS yaklaĆımı çok dĂŒĆĂŒk besleme gerilimlerinde çalıĆan çok dĂŒĆĂŒk gĂŒĂ§ tĂŒketimli devrelere baĆarıyla uygulanmıĆtır. Tasarlanan devreler arasında OTA, OP-AMP, CCII gibi analog aktif yapı blokları, çarpma devresi, sadece-MOS yapılar gibi devreler bulunmaktadır. Tasarlanan devreler SPICE benzetimleri ile doÄrulanmıĆtır. Ä°leri yönde gövde kutuplamaya baÄlı olarak DTMOS transistorun yapısından kaynaklanan, efektif olarak dĂŒĆĂŒk eĆik gerilimli çalıĆma özelliÄi nedeniyle, çok dĂŒĆĂŒk gĂŒĂ§ tĂŒketimli ve çok dĂŒĆĂŒk gerilimli devrelerde DTMOS yaklaĆımının geçerli bir alternatif olduÄu bu çalıĆmayla gösterilmiĆtir. DTMOS yaklaĆımının geniĆ bir alanda çeĆitlilik gösteren analog devre yapılarında çok dĂŒĆĂŒk besleme gerilimlerinde bile kabul edilebilir bir performansla kullanılabileceÄi bulunmuĆtur.In this study, DTMOS approach to the design of ultra low-voltage and ultra low-power analog circuits, has been successfully applied to the circuits ranging from EEG filtering circuits, speech processing filters in hearing aids, multipliers, analog active building blocks: OTA, OP-AMP, CCII to MOS-only circuits. The proposed circuits are verified with SPICE simulations. It is found that in designing ultra low-voltage, ultra low-power analog circuits, DTMOS approach is a viable alternative due to its inherent characteristic of effective low threshold voltage behaviour under forward body bias. This approach can be applied to several analog application subjects with acceptable performance under even ultra low supply voltages.DoktoraPh
Exploiting the bulk-driven approach in CMOS analogue amplifier design
This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused â at the input-stage of differential pairs, at the source followers, and at the cascode devices.
For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the authorâs best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented.
The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of
the OTA exceeds 60dB using a 0.35ÎŒm CMOS technology.
The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results
Exploiting the bulk-driven approach in CMOS analogue amplifier design
This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused â at the input-stage of differential pairs, at the source followers, and at the cascode devices.
For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the authorâs best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented.
The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of
the OTA exceeds 60dB using a 0.35ÎŒm CMOS technology.
The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results