960 research outputs found
Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers
In the field of radio receivers, down-conversion methods usually rely on one (or more)
explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not
only contribute to the overall power consumption but also have an impact on area and can
compromise the receiver’s performance in terms of noise and linearity. On the other hand,
most ADCs require some sort of reference signal in order to properly digitize an analog
input signal. The implementation of this reference signal usually relies on bandgap
circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this
conventional approach, the work developed in this thesis aims to explore the viability
behind the usage of a variable reference signal. Moreover, it demonstrates that not only
can an input signal be properly digitized, but also shifted up and down in frequency,
effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver
chains can perform double-duty as both a quantizer and a mixing stage. The lesser known
charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs,
is used for a practical implementation, due to its feature of “pre-charging” the reference
signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in
a 0.13 μm CMOS technology validate the proposed technique
Design and debugging of multi-step analog to digital converters
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process
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Signal acquisition challenges in mobile systems
In recent decades, the advent of mobile computing has changed human lives by providing information that was not available in the past. The mobile computing platform opens a new door to the connected world in which various forms of hand-held and wearable systems are ubiquitous. A single mobile device plays multiple roles and shapes human lives towards a better future. In these systems, sensor-based data acquisition plays an essential role in generating and providing useful information.
The increased number of sensors is embedded in a single device in order to process various signal modalities. In practice, more than 30 data converters are required in designing a mobile system in which the data-converting blocks become among the most power-hungry components in battery-operated systems. Due to the increased variety of sensors, mobile systems are meant to face several obstacles. For example, the increased number of sensors increase system power consumption during the system operation. The increased power consumption directly affects operation time because mobile systems are powered by a limited energy source. Moreover, an increased amount of information also gives rise to bandwidth problems in communication due to the increased volume of data transmission. Also, this system design requires a larger area in a silicon die so that multiple signal paths can be placed without cross-channel interference. Therefore, the system design has presented a challenge in terms of trying to resolve the design constraints such as power consumption, bandwidth usage, storage space, and design complexity issues.
To overcome these obstacles, in this dissertation, efficient data acquisition and processing methods are investigated. Specifically, this thesis considers the problems of energy-efficient sampling and binary event detection.
This dissertation begins by presenting a new signal sampling scheme that enables higher precision signal conversion in compressed-sensing-based signal acquisition. The proposed scheme is based on the popular successive approximation register and employs a modified compressive sensing technique to increase the resolution of successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture. Circuit-level architecture is discussed to implement the proposed scheme using the SAR ADC architecture. A non-uniform quantization scheme is proposed and it improves data quality after data acquisition. The proposed scheme is expected to be used for medium- or high- frequency data conversion.
Secondly, the possibility of using fewer ADCs than channels is studied by leveraging sparse-signal representation and blind-source-separation (BSS) techniques.
In particular, this dissertation examines the problem of using a single ADC or quantizer system for digitizing multi-channel inputs. Mixing and de-mixing strategies are extensively studied for sampling frequency-sparse signals and the proposed multi-channel architecture can be easily implemented using today's analog/mixed-signal circuits.
The third part of this dissertation investigates a binary hypothesis testing problem. In mobile devices such as smartphones and tablet PCs, a major portion of energy is consumed in user interfaces (LCD display and touch input processing). For accurate detection and better user interface, energy-efficient sensing and detection schemes are necessary to manage multiple sensor inputs. A highly efficient detection scheme is presented that can detect binary events reliably with a fraction of the energy consumption required in the conventional energy detection.Electrical and Computer Engineerin
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Design Techniques for High-Performance SAR A/D Converters
The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs.
ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption.
Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s.
The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew
calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology
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Built-in-self-test and foreground calibration of SAR ADCs
This thesis explores the scope of ‘Built-in-Self-Test’(BIST) schemes to reduce the time cost complexity associated with the production tests for static linearity errors in Successive Approximation (SAR) ADCs. In this regard, an on-chip implementation of the ‘Stimulus Based Error Identification and Removal’ (SEIR) method [1] is sought to be pursued. As an extension, it is proposed that the estimated ADC non-linearities may then be suitably calibrated to achieve higher resolution. A brief review of the testing and calibration algorithm is undertaken. Further, this work elaborates on the design of a prototype front-end test generator and a buffer interface to calibrate a 10MHz 14 bit redundant SAR ADC in the TSMC 180nm process. Simulation results validating the circuit implementation of the integrated front-end system have been presented.Electrical and Computer Engineerin
Design Techniques for High Speed Low Voltage and Low Power Non-Calibrated Pipeline Analog to Digital Converters
The profound digitization of modern microelectronic modules made Analog-to-
Digital converters (ADC) key components in many systems. With resolutions up to
14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for
a wide range of applications such as instrumentation, communications and consumer
electronics. However, while past work focused on enhancing the performance of the
pipeline ADC from an architectural standpoint, little has been done to individually
address its fundamental building blocks. This work aims to achieve the latter by
proposing design techniques to improve the performance of these blocks with minimal
power consumption in low voltage environments, such that collectively high
performance is achieved in the pipeline ADC.
Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as
an enhancement to the general performance of the conventional folded cascode. Tested
in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary
Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the
bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon
area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage
environments using a dual level common mode feedback (CMFB) circuit, and amplifier
differential offsets up to 50mV are effectively cancelled. Together with the RFC, the
dual level CMFB was used to implement a sample and hold amplifier driving a singleended
load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is
achieved. Finally a power conscious technique is proposed to reduce the kickback noise
of dynamic comparators without resorting to the use of pre-amplifiers. When all
techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in
Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2
effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal.
The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to
recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline
ADC uses the least power per conversion rated at 0.45pJ/conversion-step
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Designs and calibration of delay-line based ADCs
Delay line ADCs become more and more attractive with technology scaling to smaller dimensions with lower voltages. Time domain resolution can be increased by high speed delay cells. A GHz sampling rate can be easily achieved with low power. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay-line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. Thus, this dissertation addresses the linearity issue of delay line ADCs.
First, a novel 11-bit hybrid ADC using flash and delay line architectures, where a 4-bit flash ADC is followed by a 7-bit delay-line ADC, is proposed. In this structure, the noise/error of the second stage delay-line ADC is attenuated at the hybrid ADC output, such that the overall performance would not be limited by the poor linearity of the delay-line ADC. The achieved figure of merit (FOM) of 33.8 fJ/conversion-step is competitive with state-of-the-art ADCs. Furthermore, the proposed ADC inherits accuracy and high speed from the flash ADC and the delay-line ADC, respectively. The inherited advantages strongly support the scalability of the proposed ADC to provide a better performance with low power in further scaled fabrication processes.
Second, in order to remove the harmonic distortion of delay-line ADC, we present a technique which extends harmonic distortion correction (HDC) to digitally calibrate a delay-line ADC. In our simulation
results, digital calibration improves SNDR from 25.6 dB to 42.5 dB by averaging sample points, which corresponds to a 0.86 second calibration time.
Last, a multiple-pass delay line ADC is proposed to improve overall ADC performance in terms of speed and resolution. In this structure, a multiple-pass delay cell can be early triggered by the previous cell to increase speed. Also, phase interpolation is used to improve the effective number of bits. The design is designed and simulated in a commercial 40nm process technology. With 500MHz sampling rate, the multiple-pass delay line ADC achieves an SNDR of 37 dB and consumes 4.2 mW, which is competitive with other reported ADCs.Electrical and Computer Engineerin
Caratterizzazione dello spazio architetturale di un amplificatore transconduttivo
Il presente lavoro di tesi affronta il problema della progettazione analogica a livello di sistema studiando un convertitore analogico/digitale di tipo pipeline ad elevate prestazioni in tecnologia CMOS a 0.13 um. Più specificamente, viene studiato l’amplificatore interstadio al fine di valutare l’ottimalità delle specifiche richieste nel progetto originale. Viene applicata una metodologia di progetto basata sulla esplorazione e caratterizzazione dello spazio architetturale di interesse, volta alla creazione di una libreria (Piattaforma Analogica) che racchiuda sia modelli di prestazioni dell’ amplificatore sia modelli comportamentali dello stesso da utilizzarsi per progettazione ad alto livello. Inizialmente, viene effettuata un’ analisi del primo stadio del convertitore pipeline volta a ricavare le specifiche del blocco amplificatore. La metodologia prevede un campionamento dello spazio delle prestazioni attraverso simulazione di configurazioni generate perturbando il progetto originale. Al fine di specificare lo spazio di campionamento, vengono ricavate delle relazioni che vincolano le dimensioni dei singoli dispositivi imponendo condizioni di polarizzazione, minimo guadagno e minima banda. Le relazioni vengono quindi manipolate al fine di ottenere uno schema valutativo, basato su MATLAB/Ocean, in grado di generare configurazioni casuali del circuito che rispettano le relazioni stesse. Un insieme di indici di prestazione viene ricavato dai dati delle simulazioni cui si ricorre dato lo scarso potere predittivo dei modelli analitici. Infatti, con le moderne tecnologie CMOS i parametri di merito sono legati alle dimensioni dei dispositivi attraverso equazioni non esprimibili in forma analitica. Gli indici di prestazione vengono utilizzati per la creazione di un modello di prestazione il cui scopo è di vincolare i parametri del modello comportamentale corrispondente a valori effettivamente ottenibili dall’architettura prescelta. Tale modello di prestazione può essere utilizzato per selezionare, tramite ottimizzazione a livello di sistema, un insieme di specifiche ottime per l’amplificatore in esame
Alternative Methods for Non-Linearity Estimation in High-Resolution Analog-to-Digital Converters
The evaluation of the linearity performance of a high resolution Analog-to-
Digital Converter (ADC) by the Standard Histogram method is an outstanding
challenge due to the requirement of high purity of the input signal and
the high number of output data that must be acquired to obtain an acceptable
accuracy on the estimation. These requirements become major application
drawbacks when the measures have to be performed multiple times
within long test flows and for many parts, and under an industrial environment
that seeks to reduce costs and lead times as is the case in the New
Space sector. This thesis introduces two alternative methods that succeed
in relaxing the two previous requirements for the estimation of the Integral
Nonlinearity (INL) parameter in ADCs. The methods have been evaluated
by estimating the Integral Non-Linearity pattern by simulation using realistic
high-resolution ADC models and experimentally by applying them to real
high performance ADCs.
First, the challenge of applying the Standard Histogram method for the
evaluation of static parameters in high resolution ADCs and how the drawbacks
are accentuated in the New Space industry is analysed, being a highly
expensive method for an industrial environment where cost and lead time
reduction is demanded. Several alternative methods to the Standard Histogram
for estimating Integral Nonlinearity in high resolution ADCs are reviewed
and studied. As the number of existing works in the literature is very
large and addressing all of them is a challenge in itself, only those most relevant
to the development of this thesis have been included. Methods based
on spectral processing to reduce the number of data acquired for the linearity
test and methods based on a double histogram to be able to use generators
that do not meet the the purity requirement against the ADC to be tested are
further analysed.
Two novel contributions are presented in this work for the estimation of
the Integral Nonlinearity in ADCs, as possible alternatives to the Standard
Histogram method. The first method, referred to as SSA (Simple Spectral Approach),
seeks to reduce the number of output data that need to be acquired
and focuses on INL estimation using an algorithm based on processing the
spectrum of the output signal when a sinusoidal input stimulus is used. This type of approach requires a much smaller number of samples than the Standard
Histogram method, although the estimation accuracy will depend on
how smooth or abrupt the ADC nonlinearity pattern is. In general, this algorithm
cannot be used to perform a calibration of the ADC nonlinearity error,
but it can be applied to find out between which limits it lies and what its
approximate shape is. The second method, named SDH (Simplified Double
Histogram)aims to estimate the Non-Linearity of the ADC using a poor linearity
generator. The approach uses two histograms constructed from the
two set of output data in response to two identical input signals except for a
dc offset between them. Using a simple adder model, an extended approach
named ESDH (Extended Simplified Double Histogram) addresses and corrects
for possible time drifts during the two data acquisitions, so that it can
be successfully applied in a non-stationary test environment. According to
the experimental results obtained, the proposed algorithm achieves high estimation
accuracy.
Both contributions have been successfully tested in high-resolution ADCs
with both simulated and real laboratory experiments, the latter using a commercial
ADC with 14-bit resolution and 65Msps sampling rate (AD6644 from
Analog Devices).La medida de la característica de linealidad de un convertidor analógicodigital
(ADC) de alta resolución mediante el método estándar del Histograma
constituye un gran desafío debido los requisitos de alta pureza de la señal
de entrada y del elevado número de datos de salida que deben adquirirse
para obtener una precisión aceptable en la estimación. Estos requisitos encuentran
importantes inconvenientes para su aplicación cuando las medidas
deben realizarse dentro de largos flujos de pruebas, múltiples veces y en un
gran número de piezas, y todo bajo un entorno industrial que busca reducir
costes y plazos de entrega como es el caso del sector del Nuevo Espacio. Esta
tesis introduce dos métodos alternativos que consiguen relajar los dos requisitos
anteriores para la estimación de los parámetros de no linealidad en los
ADCs. Los métodos se han evaluado estimando el patrón de No Linealidad
Integral (INL) mediante simulación utilizando modelos realistas de ADC de
alta resolución y experimentalmente aplicándolos en ADCs reales.
Inicialmente se analiza el reto que supone la aplicación del método estándar
del Histograma para la evaluación de los parámetros estáticos en ADCs
de alta resolución y cómo sus inconvenientes se acentúan en la industria del
Nuevo Espacio, siendo un método altamente costoso para un entorno industrial
donde se exige la reducción de costes y plazos de entrega. Se estudian
métodos alternativos al Histograma estándar para la estimación de la No Linealidad
Integral en ADCs de alta resolución. Como el número de trabajos es
muy amplio y abordarlos todos es ya en sí un desafío, se han incluido aquellos
más relevantes para el desarrollo de esta tesis. Se analizan especialmente los métodos basados en el procesamiento espectral para reducir el número
de datos que necesitan ser adquiridos y los métodos basados en un doble
histograma para poder utilizar generadores que no cumplen el requisito de
precisión frente al ADC a medir.
En este trabajo se presentan dos novedosas aportaciones para la estimación
de la No Linealidad Integral en ADCs, como posibles alternativas al método
estándar del Histograma. El primer método, denominado SSA (Simple Spectral
Approach), busca reducir el número de datos de salida que es necesario
adquirir y se centra en la estimación de la INL mediante un algoritmo basado
en el procesamiento del espectro de la señal de salida cuando se utiliza un
estímulo de entrada sinusoidal. Este tipo de enfoque requiere un número
mucho menor de muestras que el método estándar del Histograma, aunque
la precisión de la estimación dependerá de lo suave o abrupto que sea el patrón
de no-linealidad del ADC a medir. En general, este algoritmo no puede
utilizarse para realizar una calibración del error de no linealidad del ADC,
pero puede aplicarse para averiguar entre qué límites se encuentra y cuál
es su forma aproximada. El segundo método, denominado SDH (Simplified
Double Histogram) tiene como objetivo estimar la no linealidad del ADC utilizando
un generador de baja pureza. El algoritmo utiliza dos histogramas,
construidos a partir de dos conjuntos de datos de salida en respuesta a dos
señales de entrada idénticas, excepto por un desplazamiento constante entre
ellas. Utilizando un modelo simple de sumador, un enfoque ampliado denominado
ESDH (Extended Simplified Double Histogram) aborda y corrige
las posibles derivas temporales durante las dos adquisiciones de datos, de
modo que puede aplicarse con éxito en un entorno de prueba no estacionario.
De acuerdo con los resultados experimentales obtenidos, el algoritmo propuesto
alcanza una alta precisión de estimación.
Ambas contribuciones han sido probadas en ADCs de alta resolución
con experimentos tanto simulados como reales en laboratorio, estos últimos
utilizando un ADC comercial con una resolución de 14 bits y una tasa de
muestreo de 65Msps (AD6644 de Analog Devices)
Noise-Shaping SAR ADCs.
This work investigates hybrid analog-to-digital converters (ADCs) that combine the phenomenal energy efficiency of successive-approximation (SAR) ADCs with the resolution enhancement strategies used by noise-shaping converters. Because charge-redistribution SAR ADCs contain few active components and rely on highly digital controllers, SAR ADCs demonstrate the best energy efficiencies of all low bandwidth, moderate resolution converters (~10 bits).
SAR ADCs achieve remarkable power efficiency at low resolution, but as the resolution of the SAR ADC increases, the specifications for input-referred comparator noise become more stringent and total DAC capacitance becomes too large, which degrades both power efficiency and bandwidth. For these reasons, lower resolution, lower bandwidth applications tend to favor traditional SAR ADC architectures, while higher bandwidth, higher resolution applications tend to favor pipeline-SARs. Although the use of amplifiers in pipeline-assisted SARs relaxes the comparator noise requirements and improves bandwidth, amplifier design becomes more of a challenge in highly scaled processes with reduced supply voltages.
In this work, we explore the use of feedback and noise-shaping to enhance the resolution of SAR ADCs. Unlike pipeline-SARs, which require high-gain, linear amplifiers, noise-shaping SARs can be constructed using passive FIR filter structures. Furthermore, the use of feedback and noise-shaping reduces the impact of thermal kT/C noise and comparator noise. This work details and explores a new class of noise-shaping SARs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/113647/1/fredenbu_1.pd
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