This thesis explores the scope of ‘Built-in-Self-Test’(BIST) schemes to reduce the time cost complexity associated with the production tests for static linearity errors in Successive Approximation (SAR) ADCs. In this regard, an on-chip implementation of the ‘Stimulus Based Error Identification and Removal’ (SEIR) method [1] is sought to be pursued. As an extension, it is proposed that the estimated ADC non-linearities may then be suitably calibrated to achieve higher resolution. A brief review of the testing and calibration algorithm is undertaken. Further, this work elaborates on the design of a prototype front-end test generator and a buffer interface to calibrate a 10MHz 14 bit redundant SAR ADC in the TSMC 180nm process. Simulation results validating the circuit implementation of the integrated front-end system have been presented.Electrical and Computer Engineerin
