620 research outputs found

    An Investigative Redesign of the ECG and EMG Signal Conditioning Circuits for Two-fault Tolerance and Circuit Improvement

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    An investigation was undertaken to make the elctrocardiography (ECG) and the electromyography (EMG) signal conditioning circuits two-fault tolerant and to update the circuitry. The present signal conditioning circuits provide at least one level of subject protection against electrical shock hazard but at a level of 100 micro-A (for voltages of up to 200 V). However, it is necessary to provide catastrophic fault tolerance protection for the astronauts and to provide protection at a current level of less that 100 micro-A. For this study, protection at the 10 micro-A level was sought. This is the generally accepted value below which no possibility of microshock exists. Only the possibility of macroshock exists in the case of the signal conditioners. However, this extra amount of protection is desirable. The initial part deals with current limiter circuits followed by an investigation into the signal conditioner specifications and circuit design

    A Novel Fully Differential Second Generation Current Conveyor and Its Application as a Very High CMRR Instrumentation Amplifier

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    This paper aims to introduce a novel Fully Differential second generation Current Conveyor (FDCCII) and its application to design a novel Low Power (LP), very high CMRR, and wide bandwidth (BW) Current Mode Instrumentation Amplifier (CMIA). In the proposed application, CMRR, as the most important feature, has been greatly improved by using both common mode feed forward (CMFF) and common mode feedback (CMFB) techniques, which are verified by a perfect circuit analysis. As another unique quality, it neither needs well-matched active blocks nor matched resistors but inherently improves CMRR, BW, and power consumption hence gains an excellent matchless choice for integration. The FDCCII has been designed using 0.18 um TSMC CMOS Technology with ±1.2 V supply voltages. The simulation of the proposed FDCCII and CMIA have been done in HSPICE LEVEL 49. Simulation results for the proposed CMIA are as follow: Voltage CMRR of 216 dB, voltage CMRR BW of 300 Hz. Intrinsic resistance of X-terminals is only 45 Ω and the power dissipation is 383.4 μW.  Most favourably, it shows a constant differential voltage gain BW of 18.1 MHz for variable gains (here ranging from 0 dB to 45.7 dB for example) removing the bottleneck of constant gain-BW product of Voltage mode circuits

    A New Proposal for OFCC-based Instrumentation Amplifier

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    This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors.  The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included

    An electrocardiogram readout circuit based on CMOS operational floating current conveyor

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    Electrocardiogram (ECG) is used in diagnosing heart diseases. It is designed as integration between current-mode instrumentation amplifiers (CMIA) and low pass filter (LPF). Normal heart behavior can be identified simply by normal ECG that consists of signal while heart disorder can be recognized by having differences in the features of their corresponding ECG waveform. A novel integrated CMOS-based operational floating current conveyor (OFCC) circuit is proposed. OFCC is a five port general purpose analog building block which combines all the features of different current mode devices such as the second generation current conveyor (CCII), the current feedback operational amplifier (CFA), and the operational floating conveyor (OFC). The OFFC is modeled and simulated using UMC 130nm CMOS technology kit in Cadence with a supply voltage 1.2V. The ECG readout circuit has been designed using the proposed OFCC as a building block. The advantages of this: it is integrated, noise factor is small as the proposed OFCC has the lowest input noise voltage and the layout is simple as it is a single block that can be repeated several times

    A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

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    In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

    Low Power CMOS Electrocardiogram Amplifier Design for Wearable Cardiac Screening

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    The trend of health care screening devices in the world is increasingly towards the favor of portability and wearability. This is because these wearable screening devices are not restricting the patient’s freedom and daily activities. While the demand of low power and low cost biomedical system on chip is increasing in exponential way, the front-end electrocardiogram (ECG) amplifiers are still suffering from flicker noise for low frequency cardiac signal acquisition, 50Hz power line electromagnetic interference, and the large unstable input offsets due to the electrode-skin interface is not attached properly. In this paper, a CMOS based ECG amplifier that suitable for low power wearable cardiac screening is proposed. The amplifier adopts the highly stable folded cascode topology and later being implemented into RC feedback circuit for low frequency DC offset cancellation. By using  0.13µm CMOS technology from Silterra, the simulation results show that this front-end circuit can achieve a very low input referred noise of  1pV/Hz1/2 and high common mode rejection ratio of 174.05dB. It also gives voltage gain of 75.45dB with good power supply rejection ratio of 92.12dB. The total power consumption is only 3µW and thus suitable to be implemented with further signal processing and classification back end for low power wearable biomedical device

    Design of the fully differential operational floating conveyor and its applications

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    Analog circuits can be generally classified into two broad categories: The first one includes analog circuits operating in the voltage mode, while the second category includes those operating in the current mode. Voltage mode analog circuit’s bandwidth is highly dependent on the gain via the gain bandwidth product (GBP). To solve this problem, many current mode circuits are developed such as the second generation Current Conveyor (CCII) and the Operational Floating Conveyor (OFC). A novel concept of the Fully Differential Operational Floating Conveyor (FD-OFC) is presented for the first time, to the best of the author’s knowledge. A CMOS design for the proposed FD-OFC is introduced as an 8 (4x4) port general purpose analog building block. The FD-OFC design is implemented using two different realizations. The proposed design has the advantage of low power consumption as it operates under biasing conditions of only 1.2 V while its wide bandwidth reaches 600 MHz. These operating conditions recommend the proposed device to be integrated to a wide range of low power-wide high speed applications. The terminal behavior of the proposed device is mathematically modeled and its operation is simulated using the UMC 130 nm technology kit in Cadence environment. Differential voltage amplifier, current mode instrumentation amplifier (CMIA) and Fully Differential second generation Current Conveyor (FDCCII) are examples of the presented applications based on the proposed FD-OFC

    A Power-Efficient Bio-Potential Acquisition Device with DS-MDE Sensors for Long-Term Healthcare Monitoring Applications

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    This work describes a power-efficient bio-potential acquisition device for long-term healthcare applications that is implemented using novel microelectromechanical dry electrodes (MDE) and a low power bio-potential processing chip. Using micromachining technology, an attempt is also made to enhance the sensing reliability and stability by fabricating a diamond-shaped MDE (DS-MDE) that has a satisfactory self-stability capability and superior electric conductivity when attached onto skin without any extra skin tissue injury technology. To acquire differential bio-potentials such as ECG signals, the proposed processing chip fabricated in a standard CMOS process has a high common mode rejection ratio (C.M.R.R.) differential amplifier and a 12-bit analog-to-digital converter (ADC). Use of the proposed system and integrate simple peripheral commercial devices can obtain the ECG signal efficiently without additional skin tissue injury and ensure continuous monitoring more than 70 hours with a 400 mAh battery

    Real-Time Telemetry System for Amperometric and Potentiometric Electrochemical Sensors

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    A real-time telemetry system, which consists of readout circuits, an analog-to-digital converter (ADC), a microcontroller unit (MCU), a graphical user interface (GUI), and a radio frequency (RF) transceiver, is proposed for amperometric and potentiometric electrochemical sensors. By integrating the proposed system with the electrochemical sensors, analyte detection can be conveniently performed. The data is displayed in real-time on a GUI and optionally uploaded to a database via the Internet, allowing it to be accessed remotely. An MCU was implemented using a field programmable gate array (FPGA) to filter noise, transmit data, and provide control over peripheral devices to reduce power consumption, which in sleep mode is 70 mW lower than in operating mode. The readout circuits, which were implemented in the TSMC 0.18-μm CMOS process, include a potentiostat and an instrumentation amplifier (IA). The measurement results show that the proposed potentiostat has a detectable current range of 1 nA to 100 μA, and linearity with an R2 value of 0.99998 in each measured current range. The proposed IA has a common-mode rejection ratio (CMRR) greater than 90 dB. The proposed system was integrated with a potentiometric pH sensor and an amperometric nitrite sensor for in vitro experiments. The proposed system has high linearity (an R2 value greater than 0.99 was obtained in each experiment), a small size of 5.6 cm × 8.7 cm, high portability, and high integration
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