Circuit simulation using distributed waveform relaxation techniques

Simulation plays an important role in the design of integrated circuits. Due to high costs and large delays involved in their fabrication, simulation is commonly used to verify functionality and to predict performance before fabrication. This thesis describes analysis, implementation and performance evaluation of a distributed memory parallel waveform relaxation technique for the electrical circuit simulation of MOS VLSI circuits. The waveform relaxation technique exhibits inherent parallelism due to the partitioning of a circuit into a number of sub-circuits. These subcircuits can be concurrently simulated on parallel processors. Different forms of parallelism in the direct method and the waveform relaxation technique are studied. An analysis of single queue and distributed queue approaches to implement parallel waveform relaxation on distributed memory machines is performed and their performance implications are studied. The distributed queue approach selected for exploiting the coarse grain parallelism across sub-circuits is described. Parallel waveform relaxation programs based on Gauss-Seidel and Gauss-Jacobi techniques are implemented using a network of eight Transputers. Static and dynamic load balancing strategies are studied. A dynamic load balancing algorithm is developed and implemented. Results of parallel implementation are analyzed to identify sources of bottlenecks. This thesis has demonstrated the applicability of a low cost distributed memory multi-computer system for simulation of MOS VLSI circuits. Speed-up measurements prove that a five times improvement in the speed of calculations can be achieved using a full window parallel Gauss-Jacobi waveform relaxation algorithm. Analysis of overheads shows that load imbalance is the major source of overhead and that the fraction of the computation which must be performed sequentially is very low. Communication overhead depends on the nature of the parallel architecture and the design of communication mechanisms. The run-time environment (parallel processing framework) developed in this research exploits features of the Transputer architecture to reduce the effect of the communication overhead by effectively overlapping computation with communications, and running communications processes at a higher priority. This research will contribute to the development of low cost, high performance workstations for computer-aided design and analysis of VLSI circuits

Multiscale simulation of frequency dependent line models and network equivalents

The evaluation of power systems encompasses phenomenon of distinct timeframes and so leads to the adoption of different simulation tools. For instance, fast transients related to switching maneuvers require time-steps of microseconds while slow transients, related to energy exchange between generators, demand timesteps of milliseconds. However, the need to assess conditions where slow frequency oscillations might be combined with fast transients is becoming more common. This research evaluates the use of frequency dependent admittance-based models in the development of multiscale algorithms for phase-coordinate modeling of overhead lines, subsea cables and frequency dependent network equivalents. Unlike the modeling with the Method of Characteristics, the direct fitting of the nodal admittance matrix and two alternative schemes are considered to cope with the trade-off between time-step and traveling times, namely: the Folded Line Equivalent and Idempotent Decomposition. The concept of Latency is also addressed in a distinct way to provide more efficient realization frequency dependent models to allow the so-called multirate simulation. The major advantage of the designed models is the straightforward implementation in EMTP-like programs such as PSCAD, EMTP-RV and ATP since they attain the same Norton-type structure. In addition, dynamic phasors allowed the unification of electromagnetic and electromechanical modeling into a single model. Both numerical performance and accuracy of the proposed schemes are evaluated through several test cases. The Method of Characteristics and the Numerical Laplace Transform are used for comparison. The computational burden is considerably reduced without significant loss of accuracy and with no numerical oscillations or discontinuities in the waveforms.A análise de sistemas elétricos engloba fenômenos com diferentes constantes de tempo, o que acarreta na utilização de diversas ferramentas de simulação. Como exemplo, transitórios rápidos envolvendo surtos de manobra demandam passos de integração na ordem de microssegundos enquanto para transitórios lentos, advindos da troca de energia entre geradores, adotam-se passos de integração de milissegundos. O presente trabalho investiga a utilização de modelos baseados em matrizes de admitância variantes na frequência para representação de linhas de transmissão aéreas, cabos submarinos e equivalentes de rede em coordenadas de fase para o desenvolvimento de algoritmos para simulação multiescala. Ao invés da utilização do Método das Características, a matriz de admitância nodal e duas decomposições alternativas são consideradas de modo a contornar a limitação do passo de integração em função do tempo de tráfego de linhas, a saber: o Folded Line Equivalent e a Decomposição Idempotente. O conceito de Latência será também investigado de modo a prover uma realização mais eficiente de modelos variantes na frequência. As formulações desenvolvidas neste trabalho encontram aplicação imediata em programas para simulação de transitórios eletromagnéticos, tais como PSCAD, EMTP-RV e ATP dado que é mantida a representação através dos equivalentes de Norton. Por meio de fasores dinâmicos, torna-se viável a representação de fenômenos eletromagnéticos e eletromecânicos com o mesmo modelo computacional. Casos teste são empregados na avaliação do desempenho e precisão das formulações propostas. O Método das Características e a transformada numérica de Laplace são utilizados para fins de comparação. Com reduzido esforço computacional, resultados com excelente precisão são obtidos sem a presença de oscilações numéricas ou descontinuidades nas formas de onda

Transformations of High-Level Synthesis Codes for High-Performance Computing

Specialized hardware architectures promise a major step in performance and energy efficiency over the traditional load/store devices currently employed in large scale computing systems. The adoption of high-level synthesis (HLS) from languages such as C/C++ and OpenCL has greatly increased programmer productivity when designing for such platforms. While this has enabled a wider audience to target specialized hardware, the optimization principles known from traditional software design are no longer sufficient to implement high-performance codes. Fast and efficient codes for reconfigurable platforms are thus still challenging to design. To alleviate this, we present a set of optimizing transformations for HLS, targeting scalable and efficient architectures for high-performance computing (HPC) applications. Our work provides a toolbox for developers, where we systematically identify classes of transformations, the characteristics of their effect on the HLS code and the resulting hardware (e.g., increases data reuse or resource consumption), and the objectives that each transformation can target (e.g., resolve interface contention, or increase parallelism). We show how these can be used to efficiently exploit pipelining, on-chip distributed fast memory, and on-chip streaming dataflow, allowing for massively parallel architectures. To quantify the effect of our transformations, we use them to optimize a set of throughput-oriented FPGA kernels, demonstrating that our enhancements are sufficient to scale up parallelism within the hardware constraints. With the transformations covered, we hope to establish a common framework for performance engineers, compiler developers, and hardware developers, to tap into the performance potential offered by specialized hardware architectures using HLS

Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.Comment: submitted to IEEE transactions on signal processin

Custom Integrated Circuits

Contains reports on twelve research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAAL03-86-K-0002)Joint Services Electronics Program (Contract DAAL03-89-C-0001)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI Semiconductor, Inc.U.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryNational Science Foundation (Grant MIP 84-07285)National Science Foundation (Grant MIP 87-14969)Battelle LaboratoriesNational Science Foundation (Grant MIP 88-14612)DuPont CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation (Grant MIP-88-58764