Performance evaluation of data-driven techniques for the softwarized and agnostic management of an N×N photonic switch

The emerging Software Defined Networking (SDN) paradigm paves the way for flexible and automatized management at each layer. The SDN-enabled optical network requires each network element’s software abstraction to enable complete control by the centralized network controller. Nowadays, silicon photonics due to its low energy consumption, low latency, and small footprint is a promising technology for implementing photonic switching topologies, enabling transparent lightpath routing in re-configurable add-drop multiplexers. To this aim, a model for the complete management of photonic switching systems’ control states is fundamental for network control. Typically, photonics-based switches are structured by exploiting the modern technology of Photonic Integrated Circuit (PIC) that enables complex elementary cell structures to be driven individually. Thus PIC switches’ control states are combinations of a large set of elementary controls, and their definition is a challenging task. In this scenario, we propose the use of several data-driven techniques based on Machine Learning (ML) to model the control states of a PIC N×N photonic switch in a completely blind manner. The proposed ML-based techniques are trained and tested in a completely topological and technological agnostic way, and we envision their application in a real-time control plane. The proposed techniques’ scalability and accuracy are validated by considering three different switching topologies: the Honey-Comb Rearrangeable Optical Switch (HCROS), Spanke-Beneš, and the Beneš network. Excellent results in terms of predicting the control states are achieved for all of the considered topologies

Machine Learning for Multi-Layer Open and Disaggregated Optical Networks

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Optimal control of Beneš optical networks assisted by machine learning

Optimal control of Beneˇs optical networks assisted by machine learning Ihtesham Khana, Lorenzo Tunesia, Muhammad Umar Masooda, Enrico Ghillinob, Paolo Bardellaa, Andrea Carenaa, and Vittorio Curria aPolitecnico di Torino, Corso Duca degli Abruzzi 24, Torino, Italy bSynopsys Inc., Executive Blvd 101, Ossining, New York, USA ABSTRACT Beneˇs networks represent an excellent solution for the routing of optical telecom signals in integrated, fully reconfigurable networks because of their limited number of elementary 2x2 crossbar switches and their non- blocking properties. Various solutions have been proposed to determine a proper Control State (CS) providing the required permutation of the input channels; since for a particular permutation, the choice is not unique, the number of cross-points has often been used to estimate the cost of the routing operation. This work presents an advanced version of this approach: we deterministically estimate all (or a reasonably large number of) the CSs corresponding to the permutation requested by the user. After this, the retrieved CSs are exploited by a data- driven framework to predict the Optical Signal to Noise Ratio (OSNR) penalty for each CS at each output port, finally selecting the CS providing minimum OSNR penalty. Moreover, three different data-driven techniques are proposed, and their prediction performance is analyzed and compared. The proposed approach is demonstrated using 8x8 Beneˇs architecture with 20 ring resonator-based crossbar switches. The dataset of 1000 OSNRs realizations is generated synthetically for random combinations of the CSs using Synopsys® Optsim™ simulator. The computational cost of the proposed scheme enables its real-time operation in the field

SerIOS: Enhancing Hardware Security in Integrated Optoelectronic Systems

Silicon photonics (SiPh) has different applications, from enabling fast and high-bandwidth communication for high-performance computing systems to realizing energy-efficient optical computation for AI hardware accelerators. However, integrating SiPh with electronic sub-systems can introduce new security vulnerabilities that cannot be adequately addressed using existing hardware security solutions for electronic systems. This paper introduces SerIOS, the first framework aimed at enhancing hardware security in optoelectronic systems by leveraging the unique properties of optical lithography. SerIOS employs cryptographic keys generated based on imperfections in the optical lithography process and an online detection mechanism to detect attacks. Simulation and synthesis results demonstrate SerIOS's effectiveness in detecting and preventing attacks, with a small area footprint of less than 15% and a 100% detection rate across various attack scenarios and optoelectronic architectures, including photonic AI accelerators

Design techniques to enhance low-power wireless communication soc with reconfigurability and wake up radio

Nowadays, Internet of things applications are increasing, and each end-node has more demanding requirements such as energy efficiency and speed. The thesis proposes a heterogeneous elaboration unit for smart power applications, that consists of an ultra-low-power microcontroller coupled with a small (around 1k equivalent gates) soft-core of embedded FPGA. This digital system is implemented in 90-nm BCD technology of STMicroelectronics, and through the analysis presented in this thesis proves to have good performance in terms of power consumption and latency. The idea is to increase the system performance exploiting the embedded FPGA to managing smart power tasks. For the intended applications, a remarkable computational load is not required, it is just required the implementation of simple finite state machines, since they are event-driven applications. In this way, while the microcontroller deals with other system computations such as high-level communications, the eFPGA can efficiently manage smart power applications. An added value of the proposed elaboration unit is that a soft-core approach is applied to the whole digital system including the eFPGA, and hence, it is portable to different technologies. On the other hand, the configurability improvement has a straightforward drawback of about a 20–27% area overhead. The eFPGA usage to manage smart power applications, allows the system to reduce the required energy per task from about 400 to around 800 times compared to a processor implementation. The eFPGA utilization improves also the latency performance of the system reaching from 8 to 145 times less latency in terms of clock cycles. The thesis also introduces the architecture of a nano-watt wake-up radio integrated circuit implemented in 90-nm BCD technology of STMicroelectronics. The wake-up radio is an auxiliary always-on radio for medium-range applications that allows the IoT end-nodes to drastically reduce the power consumption during the node idle-listening communication phase

Automatic Management of N × N Photonic Switch Powered by Machine Learning in Software-Defined Optical Transport

Optical networking is fast evolving towards the applications of the Software-defined Networking (SDN) paradigm down to the (Wavelength-division Multiplexing) WDM transport layer for cost-effective and flexible infrastructure management. Optical SDN requires each network element's software abstraction to enable full control by the centralized network controller. Nowadays, modern network elements, especially photonic switching systems, are developed by exploiting the fast-emerging technology of Photonic Integrated Circuit (PIC) that consists of complex fabrics of elementary units that can be driven individually using a large set of elementary controls. In this work, we focus on modeling the elementary control states of the topological structures behind PIC ${N} \times {N}$ switches under a fully blind approach based on Machine Learning (ML) techniques. The ML agent's training and testing datasets are obtained synthetically by software simulation of the photonic switch structure. The proposed technique's scalability and accuracy are validated by considering different dimensions ${N}$ and applying it to two different switching topologies: the Honey-Comb Rearrangeable Optical Switch and the Benes network. Excellent results in terms of prediction of the control states are achieved for both of the considered topologies

Spatial parallelism in the routers of asynchronous on-chip networks

State-of-the-art multi-processor systems-on-chip use on-chip networks as their communication fabric. Although most on-chip networks are implemented synchronously, asynchronous on-chip networks have several advantages over their synchronous counterparts. Timing division multiplexing (TDM) flow control methods have been utilized in asynchronous on-chip networks extensively. The synchronization required by TDM leads to significant speed penalties. Compared with using TDM methods, spatial parallelism methods, such as the spatial division multiplexing (SDM) flow control method, achieve better network throughput with less area overhead.This thesis proposes several techniques to increase spatial parallelism in the routers of asynchronous on-chip networks.Channel slicing is a new pipeline structure that alleviates the speed penalty by removing the synchronization among bit-level data pipelines. It is also found out that the lookahead pipeline using early evaluated acknowledgement can be used in routers to further improve speed.SDM is a new flow control method proposed for asynchronous on-chip networks. It improves network throughput without introducing synchronization among buffers of different frames, which is required by TDM methods. It is also found that the area overhead of SDM is smaller than the virtual channel (VC) flow control method -- the most used TDM method. The major design problem of SDM is the area consuming crossbars. A novel 2-stage Clos switch structure is proposed to replace the crossbar in SDM routers, which significantly reduces the area overhead. This Clos switch is dynamically reconfigured by a new asynchronous Clos scheduler.Several asynchronous SDM routers are implemented using these new techniques. An asynchronous VC router is also reproduced for comparison. Performance analyses show that the SDM routers outperform the VC router in throughput, area overhead and energy efficiency.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Spatial parallelism in the routers of asynchronous on-chip networks

State-of-the-art multi-processor systems-on-chip use on-chip networks as their communication fabric. Although most on-chip networks are implemented synchronously, asynchronous on-chip networks have several advantages over their synchronous counterparts. Timing division multiplexing (TDM) flow control methods have been utilized in asynchronous on-chip networks extensively. The synchronization required by TDM leads to significant speed penalties. Compared with using TDM methods, spatial parallelism methods, such as the spatial division multiplexing (SDM) flow control method, achieve better network throughput with less area overhead.This thesis proposes several techniques to increase spatial parallelism in the routers of asynchronous on-chip networks.Channel slicing is a new pipeline structure that alleviates the speed penalty by removing the synchronization among bit-level data pipelines. It is also found out that the lookahead pipeline using early evaluated acknowledgement can be used in routers to further improve speed.SDM is a new flow control method proposed for asynchronous on-chip networks. It improves network throughput without introducing synchronization among buffers of different frames, which is required by TDM methods. It is also found that the area overhead of SDM is smaller than the virtual channel (VC) flow control method -- the most used TDM method. The major design problem of SDM is the area consuming crossbars. A novel 2-stage Clos switch structure is proposed to replace the crossbar in SDM routers, which significantly reduces the area overhead. This Clos switch is dynamically reconfigured by a new asynchronous Clos scheduler.Several asynchronous SDM routers are implemented using these new techniques. An asynchronous VC router is also reproduced for comparison. Performance analyses show that the SDM routers outperform the VC router in throughput, area overhead and energy efficiency.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Optical Wireless Data Center Networks

Bandwidth and computation-intensive Big Data applications in disciplines like social media, bio- and nano-informatics, Internet-of-Things (IoT), and real-time analytics, are pushing existing access and core (backbone) networks as well as Data Center Networks (DCNs) to their limits. Next generation DCNs must support continuously increasing network traffic while satisfying minimum performance requirements of latency, reliability, flexibility and scalability. Therefore, a larger number of cables (i.e., copper-cables and fiber optics) may be required in conventional wired DCNs. In addition to limiting the possible topologies, large number of cables may result into design and development problems related to wire ducting and maintenance, heat dissipation, and power consumption. To address the cabling complexity in wired DCNs, we propose OWCells, a class of optical wireless cellular data center network architectures in which fixed line of sight (LOS) optical wireless communication (OWC) links are used to connect the racks arranged in regular polygonal topologies. We present the OWCell DCN architecture, develop its theoretical underpinnings, and investigate routing protocols and OWC transceiver design. To realize a fully wireless DCN, servers in racks must also be connected using OWC links. There is, however, a difficulty of connecting multiple adjacent network components, such as servers in a rack, using point-to-point LOS links. To overcome this problem, we propose and validate the feasibility of an FSO-Bus to connect multiple adjacent network components using NLOS point-to-point OWC links. Finally, to complete the design of the OWC transceiver, we develop a new class of strictly and rearrangeably non-blocking multicast optical switches in which multicast is performed efficiently at the physical optical (lower) layer rather than upper layers (e.g., application layer). Advisors: Jitender S. Deogun and Dennis R. Alexande