Analisis Unjuk Kerja Flow Control pada Network On Chip dalam Beberapa Kondisi Jaringan

Network on Chip ialah teknik yang digunakan di System on Chip sebagai pengganti shared bus dan direct point – to – point. Pada Network on Chip terdapat parameter desain dan parameter performansi jaringan. Penentuan parameter desain dan perkembangan dari jaringan dapat menimbulkan permasalahan pada jaringan seperti congestion dan saturasi yang menyebabkan paket hilang. Congestion dapat diatasi dengan menggunakan flow control yang tepat. Pada penelitian ini dilakukan analisis terhadap tiga teknik flow control yaitu Stall / Go , Ack / Nack serta Dynamic Multi Level yang diterapkan pada dua model jaringan. Model jaringan yang pertama untuk mengamati pengaruh flow control terhadap saturasi jaringan dan model kedua untuk mengamati pengaruh flow control terhadap Perubahan parameter desain dan mendapatkan teknik flow control yang paling optimal dan pengaruh Perubahan parameter desain terhadap parameter performansi jaringan. Dari hasil penelitian, jaringan yang menggunakan flow control tidak mengalami saturasi. Dimana flow control Stall / Go merupakan flow control terbaik dalam meningkatkan throughput sebesar 21.08% , 65.33%, 151% dan 13.37% , menurunkan delay sebesar 407.85, 606.03, 1631.95, 322.59 cycles, menurunkan penggunaan daya sebesar 68.67%, 61.33%, 49.93%, 68.22% untuk masing – masing Perubahan ukuran jaringan, Perubahan packet injection rate, Perubahan ukuran paket dan Perubahan ukuran buffer

Analisis Unjuk Kerja Flow Control pada Network on Chip dalam Beberapa Kondisi Jaringan

Network on Chip ialah teknik yang digunakan di System on Chip sebagai pengganti shared bus dan direct point – to – point. Pada Network on Chip terdapat parameter desain dan parameter performansi jaringan. Penentuan parameter desain dan perkembangan dari jaringan dapat menimbulkan permasalahan pada jaringan seperti congestion dan saturasi yang menyebabkan paket hilang. Congestion dapat diatasi dengan menggunakan flow control yang tepat. Pada penelitian ini dilakukan analisis terhadap tiga teknik flow control yaitu Stall / Go , Ack / Nack serta Dynamic Multi Level yang diterapkan pada dua model jaringan. Model jaringan yang pertama untuk mengamati pengaruh flow control terhadap saturasi jaringan dan model kedua untuk mengamati pengaruh flow control terhadap perubahan parameter desain dan mendapatkan teknik flow control yang paling optimal dan pengaruh perubahan parameter desain terhadap parameter performansi jaringan. Dari hasil penelitian, jaringan yang menggunakan flow control tidak mengalami saturasi. Dimana flow control Stall / Go merupakan flow control terbaik dalam meningkatkan throughput sebesar 21.08% , 65.33%, 151% dan 13.37% , menurunkan delay sebesar 407.85, 606.03, 1631.95, 322.59 cycles, menurunkan penggunaan daya sebesar 68.67%, 61.33%, 49.93%, 68.22% untuk masing – masing perubahan ukuran jaringan, perubahan packet injection rate, perubahan ukuran paket dan perubahan ukuran buffer

Fault-Tolerant Circuits and Interconnects for Biomedical Implantable Devices

Proyecto de Investigación (Código 1360014) Instituto Tecnológico de Costa Rica. Vicerrectoría de Investigación y Extensión (VIE). Escuela de Ingeniería Electrónica, 2020Los dispositivos médicos implantables (IMDs) son sistemas críticos para la seguridad con requerimientos de potencia muy bajos, los cuales se utilizan para el tratamiento a largo plazo de diferentes condiciones médicas. IMDs utilizan un número de componentes cada vez más elevado (sensores, actuadores, procesadores, bloques de memoria), que tienen que comunicarse entre ellos en un Sistema en Chip (SoC). En este proyecto, diferentes tipos de interconexiones (punto a punto, bus, red en chip) fueron evaluadas considerando su tolerancia a fallas, consumo de potencia y capacidades de comunicación. Como parte de los productos se desarrolló una base de datos escalable sobre sistemas médicos implantables reportados en la literatura hasta el año 2018, con el fin de conocer el estado del arte y las tendencias sobre la incorporación de sistemas electrónicos en este tipo de solución. Basado en este estudio inicial, se procedió a proponer un marco de trabajo de evaluación de interconexiones, el que incorpora un generador de topologías y el flujo de diseño para evaluar estas topologías en términos de potencia y tolerancia a fallas a nivel de simulación, junto con la propuesta de una métrica para comparar diferentes arquitecturas a nivel de pre-síntesis (previo a la consolidación del diseño). Por último, un diseño e implementación a nivel de circuito integrado (IC) de una solución de interconexiones ajustada a IMDs se incorporó en el diseño de un microprocesador a la medida. Este proyecto se desarrolló en el marco de la cooperación con el Centro Médico Erasmus (Erasmus MC) en los Países Bajos y la Universidad Católica del Uruguay

DDRNoC: Dual Data-Rate Network-on-Chip

This article introduces DDRNoC, an on-chip interconnection network capable of routing packets at Dual Data Rate. The cycle time of current 2D-mesh Network-on-Chip routers is limited by their control as opposed to the datapath (switch and link traversal), which exhibits significant slack. DDRNoC capitalizes on this observation, allowing two flits per cycle to share the same datapath. Thereby, DDRNoC achieves higher throughput than a Single Data Rate (SDR) network. Alternatively, using lower voltage circuits, the above slack can be exploited to reduce power consumption while matching the SDR network throughput. In addition, DDRNoC exhibits reduced clock distribution power, improving energy efficiency, as it needs a slower clock than a SDR network that routes packets at the same rate. Post place and route results in 28nm technology show that, compared to an iso-voltage (1.1V) SDR network, DDRNoC improves throughput proportionally to the SDR datapath slack. Moreover, a low-voltage (0.95V) DDRNoC implementation converts that slack to power reduction offering the 1.1V SDR throughput at a substantially lower energy cost

Interconnect Fabric Reconfigurability for Network on Chip

Microprocessor architectures are evolving at a pace greater than ever before. To meet the industry’s stringent power, performance and cost demands there is a rising trend towards building heterogeneous processors with both CPU cores and off-chip components on the same chip. This is known as a System on Chip. These systems show promising solutions including chip interconnects consisting of Network on Chips (NoCs). These NoCs are composed of routers that control traffic, and channels used to connect different components of the chip itself together. Depending on the processor core's type, specifications, and technology used, the NoC fabrics may consume anywhere ranging from 28% to 40% of the total system power. To reduce this significant power consumption, various solutions were proposed targeting CMOS technology. In this work we focus on NoC topology improvements and reconfigurability using novel VeSFET technology. The work deploys tools used to simulate full systems, such as GPGPUSIM, to evaluate the possible performance/power gains of a hybrid CMOS-VeSFET system. This hybrid system includes CMOS core and memory layers, while the NoC layer is made up of VeSFET transistors. This allows for shorter wire lengths between routers and cores, as well as it permits for extra area to include network reconfigurability features. The necessary modifications to build this hybrid system are area changes due to VeSFET additional layer, routing length changes, pipelining changes, and VeSFET technology parameter additions. The tools modifications necessary to include this system are described in further details in this thesis. The gathered data indicates great promise for the hybrid reconfigurable CMOS-VeSFET system over the conventional non-reconfigurable CMOS system. It is demonstrated that the hybrid VeSFET system has both a power decrease of approximately 57.0% and a performance increase of approximately 50.2%

DDRNoC: Dual Data-Rate Network-on-Chip

This paper introduces DDRNoC, an on-chip interconnection network able to route packets at Dual Data Rate. The cycle time of current 2D-mesh Network-on-Chip routers is limited by their control as opposed to the datapath (switch and link traversal) which exhibits significant slack. DDRNoC capitalizes on this observation allowing two flits per cycle to share the same datapath. Thereby, DDRNoC achieves higher throughput than a Single Data Rate (SDR) network. Alternatively, using lower voltage circuits, the above slack can be exploited to reduce power consumption while matching the SDR network throughput. In addition, DDRNoC exhibits reduced clock distribution power, improving energy efficiency, as it needs a slower clock than a SDR network that routes packets at the same rate. Post place and route results in 28 nm technology show that, compared to an iso-voltage (1.1V) SDR network, DDRNoC improves throughput proportionally to the SDR datapath slack. Moreover, a low-voltage (0.95V) DDRNoC implementation converts that slack to power reduction offering the 1.1V SDR throughput at a substantially lower energy cost

Dual Data Rate Network-on-Chip Architectures

Networks-on-Chip (NoCs) are becoming increasing important for the performance of modern multi-core systems-on-chip. The performance of current NoCs is limited, among others, by two factors: their limited clock frequency and long router pipeline. The clock frequency of a network defines the limits of its saturation throughput. However, for high throughput routers, clock is constrained by the control logic (for virtual channel and switch allocation) whereas the datapath (crossbar switch and links) possesses significant slack. This slack in the datapath wastes network throughput potential. Secondly, routers require flits to go through a large number of pipeline stages increasing packet latency at low traffic loads. These stages include router resource allocation, switch traversal (ST) and link traversal (LT). The allocation stages are used to manage contention among flits attempting to simultaneously access switch and links, and the ST stage is needed to change the routing dimension. In some cases, these stages are not needed and then requiring flits to go through them increases packet latency. The aim of this thesis is to improve NoC performance, in terms of network throughput, by removing the slack in the router datapath, and in terms of average packet latency, by enabling incoming flits to bypass, when possible, allocation and ST stages. More precisely, this thesis introduces Dual Data-Rate (DDR) NoC architectures which exploit the slack present in the NoC datapath to operate it at DDR. This requires a clock with period twice the datapath delay and removes the control logic from the critical path. DDR datapaths enable throughput higher than existing single data-rate (SDR) networks where the clock period is defined by the control logic. Additionally, this thesis supplements DDR NoC architectures with varying levels of pipeline stage bypassing capabilities to reduce low-load packet latency. In order to avoid complex logic required for bypassing from all inputs to all outputs, this thesis implements and evaluates a simplified bypassing approach. DDR NoC routers support bypassing of the allocation stage for flits propagating an in-network straight hop (i.e. East to West, North to South and vice versa) and when entering or exiting the network. Disabling bypassing during XY-turns limits its benefits, but, for most routing algorithms under low traffic loads, flits encounter at most one XY-turn on their way to the destination. Bypassing allocation stage enables incoming flits to directly initiate ST, when required conditions are met, and propagate at one cycle per hop. Furthermore, DDR NoC routers allow flits to bypass the ST stage when propagating a straight hop from the head of a specific input VC. Restricting ST bypassing from a specific VC further simplifies check logic to have clock period defined by datapath delays. Bypassing ST requires dedicated bypass paths from non-local input ports to opposite output ports. It enables flits to propagate half a cycle per hop. This thesis shows that compared to current state-of-the-art SDR NoCs, operating router’s datapath at DDR improves throughput by up to 20%. Adding to a DDR NoC an allocation bypassing mechanism for straight hops reduces its packet latency by up to 45%, while maintaining the DDR throughput advantage. Enhancing allocation bypassing to include flits entering and exiting the network further reduces latency by another 24%. Finally, adding ST bypassing further reduces latency by another 32%. Overall, DDR NoCs offer up to 40% lower latency and about 20% higher throughput compared to the SDR networks

Estudo sobre o consumo de energia em redes-em-chip baseadas em dispositivos nanoeletrônicos

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Elétrica, 2017.A evolução da indústria eletrônica que permitiu a implementação de arquiteturas de múltiplos núcleos foi motivada principalmente pelo consumo de energia, pois elas oferecem melhor desempenho e menor dissipação de potência do que os sistemas de processamento único. Com o aumento do número de núcleos em um único chip, a arquitetura de comunicação que interliga esses núcleos começou a ganhar importância. Assim, para resolver os problemas de interconectividade e comunicação dos sistemas em chip, a arquitetura de comunicação do tipo redes-em-chip (NoC - Network-on-Chip) tem sido proposta como uma solução altamente estruturada pela comunidade científica. Estimativas do consumo de energia das arquiteturas de comunicação devem ser realizadas no início do projeto, pois a comunicação do chip representa uma porção significante do total de energia e área consumida pelo chip. Neste contexto, este trabalho objetiva estudar sobre o consumo de energia em NoCs baseadas em dispositivos nanoeletrônicos, por meio de um modelo analítico previamente apresentado. Para obter o consumo total de energia da comunicação do chip, esse modelo utiliza como base alguns parâmetros, tais como, a energia das interconexões e dos roteadores, e a distribuição de probabilidade de comunicação. O objetivo principal deste trabalho é verificar quantitativamente qual a contribuição da nanoeletrônica na redução do consumo de energia, na arquitetura de comunicação do tipo NoC, com ênfase no estudo das interconexões. Desta forma, são feitas simulações para verificar o comportamento da latência e da energia das interconexões que conectam os roteadores da rede, em função dos nós de tecnologia, bem como, é realizada a comparação do consumo de energia entre redes com roteadores nanoeletrônicos e redes com roteadores CMOS. Por fim, é realizada uma análise comparativa entre o consumo de energia de redes com interconexões de cobre e nanotubo de carbono, utilizando roteadores nanoeletrônicos. Os resultados obtidos neste trabalho mostram que a nanoeletrônica é uma tecnologia que aparenta ser uma solução promissora na redução do consumo de energia dos futuros chips e dispositivos.The evolution of the electronic industry that allowed the implementation of multi-core architectures was motivated mainly by the energy consumption, since they offer better performance and less power dissipation than the single processing systems. With the increase in the number of cores on a single chip, the communication architecture that interconnects these cores began to gain importance. Thus, to solve the problems of interconnectivity and communication of the systems in chip, Networks-on-Chip (NoC) communication architecture has been proposed as a solution highly structured by the scientific community. Estimates of the energy consumption of communication architectures should be carried out at the beginning of the project because the communication of the chip represents a significant portion of the total energy and area consumed by the chip. In this context, this work aims to study energy consumption in NoCs based on nanoelectronic devices, through an analytical model previously presented. To obtain the total energy consumption of the chip communication, this model uses as base some parameters, such as the energy of the interconnections and the routers, and the Communication Probability Distribution. The main objective of this work is to verify quantitatively the contribution of nanoelectronics in the reduction of energy consumption in NoC communication architecture, with emphasis on the study of interconnections. In this way, simulations are performed to verify the latency and energy behavior of the interconnections that connect the routers of the network, as a function of the technology nodes, as well as, the comparison of the energy consumption between networks with nanoelectronic routers and networks with CMOS routers is made. Finally, a comparative analysis was performed between the energy consumption of networks with copper and carbon nanotube interconnections using nanoelectronic routers. The results obtained in this work show that nanoelectronics is a technology that appears to be a promising solution in reducing the energy consumption of future chips and devices