DESIGN OF RF RECEIVER COMPONENTS FOR SPACE APPLICATION SUSING SIGE BICMOS

The objective of the proposed research is to understand the behavior of components in SiGe BiCMOS technologies to the radiation environment present in space, and use such understanding to inform the design and testing of RF receiver components for space-flight applications. To evaluate the response of SiGe HBTs to various types of radiation, exposure to X-rays is performed to emulate operation in the space environment. Degradation in relevant device performance characteristics is considered as it changes with longer exposures. Then, implications of impaired device performance are demonstrated for circuit components commonly present in RF receivers for both radar and communications, and design considerations for operation in space are discussed.M.S

Deterministic dynamic element matching: an enabling technology for SoC built-in-self-test

The analog-to-digital converter (ADC) is a key building block of today\u27s high-volume systems-on-a-chip (SoCs). Built-in-self-test (BIST) is the most promising solution to testing deeply-embedded ADCs. Cost-effective stimulus source with on-chip integrability has been viewed as the bottleneck of ADC BIST, and consequentially the bottleneck of SoC BIST and BIST-based self-calibration. The deterministic dynamic element matching (DDEM) technique has been proposed as a solution to this problem;In this work, rigorous theoretical analysis is presented to show the performance of a DDEM digital-to-analog converter (DAC) as an ADC linearity test stimulus source. Guided by the insight obtained this analysis, a systematic approach for cost-effective DDEM DAC design is proposed. Two generations of DDEM DACs have been designed, fabricated, and measured. 12-bit equivalent linearity was achieved from the first DDEM DAC with 8-bit apparent resolution and less than 5-bit raw linearity after systematic error compensation. The achieved 12-bit linearity outperforms any on-chip stimulus source in literature. Based on the first design, a new DDEM DAC with 12-bit apparent resolution, 10-bit raw linearity, and 9-bit DDEM switching was designed with improved design technique. This DAC was fabricated in standard 0.5-pm CMOS technology with a core die area of 2 mm2. Clear ramp signals could be observed on an oscilloscope when the DDEM DAC was clocked at 100 MHz. Laboratory testing results confirmed that the new DDEM DAC achieved at least a 16-bit equivalent linearity; this was limited by the available instrumentation, which has 18-bit linearity. It outperforms any previously reported on-chip stimulus source in terms of ADC BIST performance by 5 bits. The robust performance, low cost, and short design cycle for on-chip implementation make DDEM an enabling technology for SoC BIST and self-calibration;Two new approaches based on DDEM are developed to further boost the die area efficiency, improving the basic DDEM approach. The first is termed segmented DDEM, and the second is dither-incorporated DDEM (DiDDEM). It has been shown through mathematical analysis and simulation that these can maintain the performance of the basic DDEM approach while greatly reducing the implementation cost

High-Performance Fpaa Design For Hierarchical Implementation Of Analog And Mixed-Signal Systems

The design complexity of today's IC has increased dramatically due to the high integration allowed by advanced CMOS VLSI process. A key to manage the increased design complexity while meeting the shortening time-to-market is design automation. In digital world, the field-programmable gate arrays (FPGAs) have evolved to play a very important role by providing ASIC-compatible design methodologies that include design-for-testability, design optimization and rapid prototyping. On the analog side, the drive towards shorter design cycles has demanded the development of high performance analog circuits that are configurable and suitable for CAD methodologies. Field-programmable analog arrays (FPAAs) are intended to achieve the benefits for analog system design as FPGAs have in the digital field. Despite of the obvious advantages of hierarchical analog design, namely short time-to-market and low non-recurring engineering (NRE) costs, this approach has some apparent disadvantages. The redundant devices and routing resources for programmability requires extra chip area, while switch and interconnect parasitics cause considerable performance degradation. To deliver a high-performance FPAA, effective methodologies must be developed to minimize those adversary effects. In this dissertation, three important aspects in the FPAA design are studied to achieve that goal: the programming technology, the configurable analog block (CAB) design and the routing architecture design. Enabled by the Laser MakelinkTM technology, which provides nearly ideal programmable switches, channel segmentation algorithms are developed to improve channel routability and reduce interconnect parasitics. Segmented routing are studied and performance metrics accounting for interconnect parasitics are proposed for performance-driven analog routing. For large scale arrays, buffer insertions are considered to further reduce interconnection delay and cross-coupling noise. A high-performance, highly flexible CAB is developed to realized both continuous-mode and switched-capacitor circuits. In the end, the implementation of an 8-bit, 50MSPS pipelined A/D converter using the proposed FPAA is presented as an example of the hierarchical analog design approach, with its key performance specifications discussed

Design of Power/Analog/Digital Systems Through Mixed-Level Simulations

In recent years the development of the applications in the field of telecommunications, data processing, control, renewable energy generation, consumer and automotive electronics determined the need for increasingly complex systems, also in shorter time to meet the growing market demand. The increasing complexity is mainly due to the mixed nature of these systems that must be developed to accommodate the new functionalities and to satisfy the more stringent performance requirements of the emerging applications. This means a more complex design and verification process. The key to managing the increased design complexity is a structured and integrated design methodology which allows the sharing of different circuit implementations that can be at transistor level and/or at a higher level (i.e.HDL languages).In order to expedite the mixed systems design process it is necessary to provide: an integrated design methodology; a suitable supporting tool able to manage the entire design process and design complexity and its successive verification.It is essential that the different system blocks (power, analog, digital), described at different level of abstraction, can be co-simulated in the same design context. This capability is referred to as mixed-level simulation.One of the objectives of this research is to design a mixed system application referred to the control of a coupled step-up dc-dc converter. This latter consists of a power stage designed at transistor-level, also including accurate power device models, and the analog controller implemented using VerilogA modules. Digital controllers are becoming very attractive in dc-dc converters for their programmability, ability to implement sophisticated control schemes, and ease of integration with other digital systems. Thus, in this dissertation it will be presented a detailed design of a Flash Analog-to-Digital Converter (ADC). The designed ADC provides medium-high resolution associated to high-speed performance. This makes it useful not only for the control application aforementioned but also for applications with huge requirements in terms of speed and signal bandwidth. The entire design flow of the overall system has been conducted in the Cadence Design Environment that also provides the ability to mixed-level simulations. Furthermore, the technology process used for the ADC design is the IHP BiCMOS 0.25 µm by using 50 GHz NPN HBT devices

High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

Digital signal processing and digital-to-analog converters for wide-band transmitters

In this thesis, the implementation methods of digital signal processing and digital-to-analog converters for wide-band transmitters are researched. With digital signal processing, the problems of analog signal processing, such as sensitivity to interference and nonidealities of the semiconductor processes, can be avoided. Also, the programmability can be implemented digitally more easily than by means of analog signal processing. During the past few years, wireless communications has evolved from analog to digital, and signal bandwidths have increased, enabling faster and faster data transmission. The evolution of semiconductor processes, decreasing linewidth and supply voltages, has decreased the size of the electronics and power dissipation, enabling the integration of larger and larger systems on single silicon chips. There is little overall benefit in decreasing linewidths to meet the needs of analog design, since it makes the design process more difficult as the device sizes cannot be scaled according to minimum linewidth and because of the decreasing supply voltage. On the other hand, the challenges of digital signal processing are related to the efficient realization of signal processing algorithms in such a way that the required area and power dissipation does not increase extensively. In this book, the problems related to digital filters, upconversion algorithms and digital-to-analog converters used in digital transmitters are researched. Research results are applied to the implementation of a transmitter for a third-generation WCDMA base-station. In addition, the theory of factors affecting the linearity and performance of digital-to-analog converters is researched, and a digital calibration algorithm for enhancement of the static linearity has been presented. The algorithm has been implemented together with a 16-bit converter; its functionality has been demonstrated with measurements.Tässä väitöskirjassa on tutkittu digitaalisen signaalinkäsittelyn toteuttamista ja digitaalisesta analogiseksi -muuntimia laajakaistaisiin lähettimiin. Digitaalisella signaalinkäsittelyllä voidaan välttää monia analogiseen signaalinkäsittelyyn liittyviä ongelmia, kuten häiriöherkkyyttä ja puolijohdeprosessien epäideaalisuuksien vaikutuksia. Myös ohjelmoitavuus on helpommin toteutettavissa digitaalisesti kuin analogisen signaalinkäsittelyn keinoin. Viime vuosina on langattomien tietoliikennejärjestelmien kehitys kulkenut analogisesta digitaaliseen, ja käytettävät signaalikaistanleveydet ovat kasvaneet mahdollistaen yhä nopeamman tiedonsiirron. Puolijohdeprosessien kehitys, kapeneva minimiviivanleveys ja pienemmät käyttöjännitteet, on pienentänyt elektroniikan kokoa ja tehonkulutusta mahdollistaen yhä suurempien kokonaisuuksien integroimisen yhdelle piisirulle. Viivanleveyksien pieneneminen ei kuitenkaan suoraan hyödytä analogiasuunnittelua, jossa piirielementtien kokoa ei välttämättä voida pienentää viivanleveyden pienentyessä, ja jossa madaltuva käyttöjännite ennemminkin hankaloittaa kuin helpottaa suunnittelua. Siksi yhä suurempi osa signaalinkäsittelystä pyritään tekemään digitaalisesti. Digitaalisen signaalinkäsittelyn ongelmat puolestaan liittyvät algoritmien tehokkaaseen toteuttamiseen siten, että piirien pinta-ala ja tehonkulutus eivät kasva liian suuriksi. Tässä kirjassa on tutkittu digitaalisessa lähettimessä tarvittavien digitaalisten suodattimien, ylössekoitusalgoritmien ja digitaalisesta analogiseksi -muuntimien toteuttamiseen liittyviä ongelmia. Tutkimustuloksia on sovellettu kolmannen sukupolven WCDMA-tukiasemalähettimen toteutuksessa. Lisäksi on tutkittu digitaalisesta analogiseksi -muuntimien lineaarisuuteen ja suorituskykyyn vaikuttavien seikkojen teoriaa, ja esitetty digitaalinen kalibrointialgoritmi muuntimen staattisen suorituskyvyn parantamiseksi. Algoritmi on toteutettu 16-bittisen muuntimen yhteydessä ja se on osoitettu toimivaksi mittauksin.reviewe

Fluorescence lifetime microscopy unveils the nanoscale organization of liposomal Doxorubicin

The present invention relates to determination of supramolecular organization in a substance including target molecules and nanocarriers at least one of which is luminescent, based on a step of collecting of lifetime decay data of at least a standard substance pure or substantially pure wherein a known organization state of the target molecules and the nanocarriers is pure or substantially pure; and a step of comparing the standard data and test data from a test substance

Correlation of Signals, Noise, and Harmonics in Parallel Analog-to-Digital Converter Arrays

Combining M analog-to-digital converters (ADC) in parallel increases the maximum signal-to-noise ratio (SNR) by a factor of M, assuming the noise is uncorrelated from one channel to the next. This allows for a significant increase in SNR over a single ADC; however, noise and harmonic correlation degrade this improvement. ADCs have three sources of noise: thermal (and other random physical processes), sampling, and quantization noise. There are two system components creating harmonics: the sampler and the quantizer. In this thesis, I determine, analytically and experimentally, the degree of correlation between signals, noise, and harmonics in a parallel ADC array. To test the analysis experimentally, I developed a 16-channel test-bed using 16-bit, state-of-the-art ADCs and 16 direct-digital synthesizers as low-noise signal sources. The test bed provides excellent signal isolation between channels and minimal digital noise to enable the measurement of very low levels of correlation. I investigated the feasibility of measuring the very high levels of signal correlation in the presence of channel nonlinearities with different measurement signals. For a completely linear channel, the channel matching is limited by noise. With nonlinearities, the ability to measure the signal correlation depends on the measurement signal. I verified that the thermal noise is uncorrelated across 16 channels as expected. I also demonstrated that sampling noise is fully correlated from channel-to-channel when a common clock drives the ADCs. Efforts to reduce the correlation using two previously developed de-correlation techniques-phase randomization and frequency offsets-successfully reduced the correlated noise by a factor of two. I then demonstrated analytically and experimentally that harmonics from quantizers are largely uncorrelated; however, harmonics from the sampler are largely correlated confirming the need for decorrelation techniques. I demonstrated the impact of the previously developed decorrelation techniques to reduce harmonic correlation and developed two new decorrelation techniques: phase cancellation and clock offsets, which offer significant advantages over phase randomization and frequency offsets. Each technique offers different levels of dynamic range improvement and complexity, allowing for a range of techniques to target the optimal level of decorrelation