Methods for testing of analog circuits

Práce se zabývá metodami pro testování lineárních analogových obvodů v kmitočtové oblasti. Cílem je navrhnout efektivní metody pro automatické generování testovacího plánu. Snížením počtu měření a výpočetní náročnosti lze výrazně snížit náklady za testování. Práce se zabývá multifrekveční parametrickou poruchovou analýzou, která byla plně implementována do programu Matlab. Vhodnou volbou testovacích kmitočtů lze potlačit chyby měření a chyby způsobené výrobními tolerancemi obvodových prvků. Navržené metody pro optimální volbu kmitočtů byly statisticky ověřeny metodou MonteCarlo. Pro zvýšení přesnosti a snížení výpočetní náročnosti poruchové analýzy byly vyvinuty postupy založené na metodě nejmenších čtverců a přibližné symbolické analýze.The thesis deals with methods for testing of linear analog circuits in the frequency domain. The goal is to develop new efficient methods for automatic test plan generation. To reduce test costs a minimum number of measurements as well as less computational demands are the fundamental aims. The thesis is focused on the multi-frequency parametric fault diagnosis which was fully implemented in the Matlab program. The fundamental problem consists in selection of test frequencies which can reduce the influences of measurement errors and errors caused by tolerances of well-working components. The proposed methods for test frequency selection were statistically verified by the MonteCarlo method. To improve the accuracy and reduce the computational complexity of fault diagnosis, the methods based on least-square techniques and approximate symbolic analysis were presented.

Multilevel Simulation Methodology for FMECA Study Applied to a Complex Cyber-Physical System

Complex systems are composed of numerous interconnected subsystems, each designed to perform specific functions. The different subsystems use many technological items that work together, as for the case of cyber-physical systems. Typically, a cyber-physical system is composed of different mechanical actuators driven by electrical power devices and monitored by sensors. Several approaches are available for designing and validating complex systems, and among them, behavioral-level modeling is becoming one of the most popular. When such cyber-physical systems are employed in mission- or safety-critical applications, it is mandatory to understand the impacts of faults on them and how failures in subsystems can propagate through the overall system. In this paper, we propose a methodology for supporting the failure mode, effects, and criticality analysis (FMECA) aimed at identifying the critical faults and assessing their effects on the overall system. The end goal is to analyze how a fault affecting a single subsystem possibly propagates through the whole cyber-physical system, considering also the embedded software and the mechanical elements. In particular, our approach allows the analysis of the propagation through the whole system (working at high level) of a fault injected at low level. This paper provides a solution to automate the FMECA process (until now mainly performed manually) for complex cyber-physical systems. It improves the failure classification effectiveness: considering our test case, it reduced the number of critical faults from 10 to 6. The remaining four faults are mitigated by the cyber-physical system architecture. The proposed approach has been tested on a real cyber-physical system in charge of driving a three-phase motor for industrial compressors, showing its feasibility and effectiveness

New Aspects of Fault Diagnosis of Nonlinear Analog Circuits

The paper is focused on nonlinear analog circuits, with the special attention paid to circuits comprising bipolar and MOS transistors manufactured in micrometer and submicrometer technology. The problem of fault diagnosis of this class of circuits is discussed, including locating faulty elements and evaluating their parameters. The paper deals with multiple parametric fault diagnosis using the simulation after test approach as well as detection and location of single catastrophic faults, using the simulation before test approach. The discussed methods are based on diagnostic test, leading to a system of nonlinear algebraic type equations, which are not given in explicit analytical form. An important and new aspect of the fault diagnosis is finding multiple solutions of the test equation, i.e. several sets of the parameters values that meet the test. Another new problems in this area are global fault diagnosis of technological parameters in CMOS circuits fabricated in submicrometer technology and testing the circuits  having multiple DC operating points. To solve these problems several methods have been recently developed, which employ  different concepts and mathematical tools of nonlinear analysis. In this paper they are sketched and illustrated.  All the discussed methods are based on the homotopy (continuation) idea. It is shown that various versions of homotopy and combinations  of the homotopy with some other mathematical algorithms lead to very powerful tools for fault diagnosis of nonlinear analog circuits.  To trace the homotopy path which allows finding multiple solutions, the simplicial method, the restart method, the theory of linear complementarity problem and Lemke's algorithm are employed. For illustration four numerical examples are given

DC tolerance analysis of electronic circuits by polyhedral circuits

1noReal equilibrium solutions of electronic circuits are affected by deviation of real characteristics of devices from their nominal values, producing the displacement of solution points from their nominal position. In this paper, a method to determine all the equilibrium regions in which real equilibrium points may fall is presented. The analysis is based on the introduction of the so-called strip characteristics that represent the characteristics of devices affected by tolerances. They are modeled by polyhedral characteristics. Different situations may occur as tolerances grow. A nominal solution point may disappear, or on the other end, some solution point not present with nominal characteristics may appear. These possible events call for a classification of the equilibrium regions in either certain or uncertain, depending on the existence or not of an equilibrium point for any choice of real characteristics. The algorithm adopts linear programming techniques and a clustering algorithm.partially_openopenPastore, StefanoPastore, Stefan

Reliability in Power Electronics and Power Systems

L'abstract è presente nell'allegato / the abstract is in the attachmen

Fault simulation for structural testing of analogue integrated circuits

In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by considering the probability of fault occurrence to generate a more realistic, weighted test metric. Two techniques to reduce the fault simulation time are described, both of which show large reductions in simulation time with little loss of accuracy. The final section of the thesis presents an accurate comparison of three test techniques and an evaluation of dynamic supply current monitoring. An increase in fault detection for dynamic supply current monitoring is obtained by removing the DC component of the supply current prior to measurement

Qualitative dynamic diagnosis of circuits

Abstract We describe ACDS, an automatic diagnostic system. ACDS is capable of diagnosing faults on analog circuits in dynamic conditions. The circuit's dynamic behavior is studied by means of a series of intrastate simulations during which the qualitative state of the circuit does not change. An acquisition board collects the value of a set of quantities corresponding to accessible test points. These measurements are converted into qualitative values and are used for two purposes: first, to determine the state of the circuit components; second, to trigger the diagnostic procedure whenever a discrepancy between observed and predicted behavior is found. The main difficulty in this phase of measurement interpretation consists in obtaining meaningful numerical-qualitative data conversion for values of quantities approaching a boundary between two different qualitative intervals. System performance has been verified through a number of simulations, which have shown the proposed approach to be efficient both in terms of localized faults and of flexibility in adapting to different circuits

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed