Shortest Paths and Steiner Trees in VLSI Routing

Routing is one of the major steps in very-large-scale integration (VLSI) design. Its task is to find disjoint wire connections between sets of points on a chip, subject to numerous constraints. This problem is solved in a two-stage approach, which consists of so-called global and detailed routing steps. For each set of metal components to be connected, global routing reduces the search space by computing corridors in which detailed routing sequentially determines the desired connections as shortest paths. In this thesis, we present new theoretical results on Steiner trees and shortest paths, the two main mathematical concepts in routing. In the practical part, we give computational results of BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics at the University of Bonn. Interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding a rectilinear Steiner minimum tree (RSMT) that --- as a secondary objective --- minimizes a signal delay related objective. Given a source we derive some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present an exact algorithm for constructing RSMTs with weighted sum of path lengths as secondary objective, and a heuristic for various secondary objectives. Computational results for industrial designs are presented. We further consider the problem of finding a shortest rectilinear Steiner tree in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if it intersects an obstacle, then no connected component of the induced subtree must be longer than a given fixed length. This kind of length restriction is motivated by its application in VLSI routing where a large Steiner tree requires the insertion of repeaters which must not be placed on top of obstacles. We show that there are optimal length-restricted Steiner trees with a special structure. In particular, we prove that a certain graph (called augmented Hanan grid) always contains an optimal solution. Based on this structural result, we give an approximation scheme for the special case that all obstacles are of rectangular shape or are represented by at most a constant number of edges. Turning to the shortest paths problem, we present a new generic framework for Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices, we label subgraphs which partition the given graph. Much better running times can be achieved if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, the algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with the routing program BonnRoute on leading-edge industrial chips. Finally, we present computational results of BonnRoute obtained on real-world VLSI chips. BonnRoute fulfills all requirements of modern VLSI routing and has been used by IBM and its customers over many years to produce more than one thousand different chips. To demonstrate the strength of BonnRoute as a state-of-the-art industrial routing tool, we show that it performs excellently on all traditional quality measures such as wire length and number of vias, but also on further criteria of equal importance in the every-day work of the designer

Despliegue óptimo de redes de distribución eléctricas soterradas usando métodos metaheurísticos y simulación

This document presents a planning model that allows optimizing the deployment of underground electrification networks for distribution considering the number of users simultaneously connected to a transformer. We present a model based on a heuristic process that seeks to reduce costs by using the resources required for a minimum cost routing on a geo-referenced scenario. The model is scalable because it allows the population density of the studied georeferenced area to be varied, that is, it adjusts to the use of resources required for different population quantities. Additionally, a simulation process is presented, articulated to the planning model using the Cymdist software, contemplating elements of a real underground electrification network, in order to verify voltage problems, failures, overloads, etc. The obtained results allow to quickly diagnose the possible deployment and routing options of underground networks for distribution, warning to decrease the times for deployment of new networks, in addition the work successfully explores the optimality principle and makes the heuristic process computationally useful. Finally, the proposal provides a road map with a view to the optimal planning of underground electrification networks for distribution.Este documento presenta un modelo de planeación que permite optimizar el despliegue de redes de electrificación soterradas para distribución considerando la cantidad de usuarios conectados simultáneamente a un transformador. Se presenta un modelo basado en un proceso heurístico que busca reducir costes por uso de recursos requeridos para un enrutamiento de mínimo costo sobre un escenario georreferenciado. El modelo es escalable pues permite que se varíe la densidad poblacional del área georreferenciada estudiada, es decir, se ajusta al uso de recursos requeridos para diferentes cantidades poblacionales. Adicionalmente se presenta un proceso de simulación articulado al modelo de planeación mediante el software Cymdist, contemplando elementos de una red de electrificación soterrada real, con la finalidad de verificar problemas de tensión, fallos, sobrecargas, etc. Los resultados obtenidos permiten diagnosticar rápidamente las posibles opciones de despliegue y enrutamiento de redes soterradas para distribución, advirtiendo disminuir los tiempos por despliegue de nuevas redes, además el trabajo explora con éxito el principio de optimalidad y hace que el proceso heurístico sea computacionalmente útil. Finalmente, la propuesta brinda un mapa de ruta con visión hacia la óptima planeación de redes de electrificación soterradas para distribución

Doctor of Philosophy

dissertationRecent breakthroughs in silicon photonics technology are enabling the integration of optical devices into silicon-based semiconductor processes. Photonics technology enables high-speed, high-bandwidth, and high-fidelity communications on the chip-scale-an important development in an increasingly communications-oriented semiconductor world. Significant developments in silicon photonic manufacturing and integration are also enabling investigations into applications beyond that of traditional telecom: sensing, filtering, signal processing, quantum technology-and even optical computing. In effect, we are now seeing a convergence of communications and computation, where the traditional roles of optics and microelectronics are becoming blurred. As the applications for opto-electronic integrated circuits (OEICs) are developed, and manufacturing capabilities expand, design support is necessary to fully exploit the potential of this optics technology. Such design support for moving beyond custom-design to automated synthesis and optimization is not well developed. Scalability requires abstractions, which in turn enables and requires the use of optimization algorithms and design methodology flows. Design automation represents an opportunity to take OEIC design to a larger scale, facilitating design-space exploration, and laying the foundation for current and future optical applications-thus fully realizing the potential of this technology. This dissertation proposes design automation for integrated optic system design. Using a buildingblock model for optical devices, we provide an EDA-inspired design flow and methodologies for optical design automation. Underlying these flows and methodologies are new supporting techniques in behavioral and physical synthesis, as well as device-resynthesis techniques for thermal-aware system integration. We also provide modeling for optical devices and determine optimization and constraint parameters that guide the automation techniques. Our techniques and methodologies are then applied to the design and optimization of optical circuits and devices. Experimental results are analyzed to evaluate their efficacy. We conclude with discussions on the contributions and limitations of the approaches in the context of optical design automation, and describe the tremendous opportunities for future research in design automation for integrated optics