Protector Control PC-AODV-BH in The Ad Hoc Networks

In this paper we deal with the protector control that which we used to secure AODV routing protocol in Ad Hoc networks. The considered system can be vulnerable to several attacks because of mobility and absence of infrastructure. While the disturbance is assumed to be of the black hole type, we purpose a control named "PC-AODV-BH" in order to neutralize the effects of malicious nodes. Such a protocol is obtained by coupling hash functions, digital signatures and fidelity concept. An implementation under NS2 simulator will be given to compare our proposed approach with SAODV protocol, basing on three performance metrics and taking into account the number of black hole malicious nodesComment: submit 15 pages, 19 figures, 1 table, Journal Indexing team, AIRCC 201

Realization of attack on SHA-1 hash function

Bakalářská práce se zabývá hašovacími funkcemi, funkcí SHA-1 a její implementací v jazyce Java. Opisuje slabiny této funkce a implementuje realizaci vybraného útoku, vedoucího k odhalení zdrojového textu nebo založeného na cíleném zfalšování haše. V této práci jsou popsané vlastnosti hašovacích funkcí, kontrukce, jejich využití. Poslední část se zabývá opisem útoku na hašovací funkci SHA-1 se složitostí 2^69.The bachelor thesis is concerned with hash functions, SHA-1 function and its implementation in Java. The thesis describes weaknesses of this function and implements the implementation of the selected attack leading to the revelation of source text or attack based on targeted falsifying hash. This work also describes characteristics of hash functions, constructions and their use. The last part deals with a description of the attack on the hash function SHA-1 with the complexity of the 2^69.

On the Exploitation of a High-throughput SHA-256 FPGA Design for HMAC

High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30% better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board)

SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

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Multi-mode operator for SHA-2 hash functions

We propose an improved implementation of the SHA-2 hash family, with minimal operator latency and reduced hardware requirements. We also propose a high frequency version at the cost of only two cycles of latency per message. Finally we present a multi-mode architecture able to perform either a SHA-384 or SHA-512 hash or to behave as two independent SHA-224 or SHA-256 operators. Such capability adds increased flexibility for applications ranging from a server running multiple streams to independent pseudorandom number generation. We also demonstrate that our architecture achieves a performance comparable to separate implementations while requiring much less hardware. Ó 2006 Elsevier B.V. All rights reserved. Keywords: FPGA; Hash function; SHA-2 family; Multi-mode operato

Multi-mode Operator for SHA-2 Hash Functions, in "Journal of Systems Architecture, Special issue on "Embedded Cryptographic Hardware"", to appear

Abstract — We propose an improved implementation of the SHA-2 hash family to include a multi-mode of operation with minimal latency and hardware requirements over the entire operator. The multi-mode architecture presented is able to perform either a SHA-384 or SHA-512 hash or to behave as two independent SHA-224 or SHA-256 operators. We also demonstrate that our architecture achieves performance comparable to separate implementations while requiring much less hardware. This could be useful for a server running multiple streams or in parallel PRNG generation. I