Two- and Three-dimensional High Performance, Patterned Overlay Multi-chip Module Technology

A two- and three-dimensional multi-chip module technology was developed in response to the continuum in demand for increased performance in electronic systems, as well as the desire to reduce the size, weight, and power of space systems. Though developed to satisfy the needs of military programs, such as the Strategic Defense Initiative Organization, the technology, referred to as High Density Interconnect, can also be advantageously exploited for a wide variety of commercial applications, ranging from computer workstations to instrumentation and microwave telecommunications. The robustness of the technology, as well as its high performance, make this generality in application possible. More encouraging is the possibility of this technology for achieving low cost through high volume usage

Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work

ATLASPIX3 Modules for Experiments at Electron-Positron Colliders

High-voltage CMOS detectors are being developed for application in High-Energy Physics. ATLASPIX3 is a full-reticle size monolithic pixel detector, consisting of 49000 pixels of dimension 50×150 μm$^2$. It has been realized in in TSI 180 nm HVCMOS technology. In view of applications at future electron-positron colliders, multi-chip-modules are built. The module design and its characterization by electrical test and radiation sources will be illustrated, including characterization of shunt regulators for serial chain powering. Lightweight long structure to support and to cool multiple-module chain are also being realized. The multi-chip-modules performance shows no degradation with respect to single-chip devices and the level of integration achieved is suitable for tracking at future e+e- accelerators

3-D MCM Technology for Miniaturisation of an Electronic System

Miniaturisation of a bulky system requires effective use and integration of modern packagingtechnology to achieve smaller size and lighter weight while consuming low power and achievinghigh speed. Using three-dimensional packaging technology, a system can be miniaturised to asmall package popularly known as system-in-a-package (SIP). Various layers of componentintegration (die or packaged) in the horizontal and vertical directions lead to a compact systemin a single package. In this paper, the development of an analog multi-chip module (MCM) isillustrated using 3-D technology. The major goals achieved using this technology are the mixedsignalintegration, arealsize reduction, and low power. A comparison is made with the systemon-a-chip (SOC) technology and their merits and demerits are also discussed

Paper Session III-C - Technology Transfer of Military Space Microprocessor Development

Over the past 11 years Phillips Laboratory has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of their programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at the USAF Phillips Laboratory to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on program to the GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by Phillips Laboratory to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two contract phases, completed in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std- 1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), is currently scheduled to complete at the end of 1997. ATIM is developing two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined in the majority of today’s DoD, NASA, and commercial satellite systems

Study on the Terahertz Nondestructive Testing Method for Multi-chip Package Inspection using a Resonant Slit-type Probe with Rounded Matching Structure

This paper presents a terahertz (THz) non-destructive testing (NDT) method for multi-chip package (MCP) inspection. A resonant slit-type probe was used to obtain high resolution while using a source in the low Th frequency region for the Th inspection. However, the conventional resonant slit structure is difficult to manufacture due to the thin thickness of the slit, as well as the problem of increasing the change of the resonance frequency and the loss of reflection due to the thickness error of the slit. A resonant slit-type probe with a rounded matching structure was proposed to improve the coupling efficiency while improving the slit thickness problem in the Th region. The proposed probe can reduce the resonance frequency change according to the thickness error while maintaining the high coupling efficiency despite the increase of the slit thickness. It is possible to reduce the FWHM by more than 40% by using the proposed structure than the conventional resonant slit structure in the foreign object detection simulation using the slit probe. A probe with a resonant frequency of 205 GHz using the proposed structure was fabricated by electroforming and compared with VNA measurement results and CST MWS simulation results. From the measurement results, it was confirmed that the proposed probe has a simple structure and high coupling efficiency. Using the pulsed THz system, the transmission characteristics of the semiconductor chip according to the polarization direction were verified, and it was confirmed that the semiconductor inspection using the THz wave was possible. A continuous (CW) THz inspection system that can be applied to process inspection has been established. A THz transceiver module based on directional coupler and a THz transceiver module based on Magic-tee have been constructed. In addition, FPGA-based high-speed lock amplifiers have been built to improve detection rates for process inspections. Standard samples were used to verify the performance of the measurement system and probes. It was confirmed that the magic-based THz transceiver module is more suitable for defect detection. The probe structure fabricated using the proposed structure was able to detect defects of 100 µm, and the high - speed signal detection module was able to detect defects stably even at a sample moving speed of 1000 mm/s. In the semiconductor chip inspection, a lateral inspection method has been proposed because the conductivity of the semiconductor surface is high. The CST Microwave Studio simulation confirmed that side inspection enabled void detection. A lateral inspection system was constructed and a void of 500 ㎛ in diameter in the multi-chip package was detected. In addition, a simple contrast-transformed image filter is applied to the detected image so that defects in the laminated structure can be easily discriminated. As a result, it is confirmed that THz wave system using the proposed probe is a new inspection tool for detecting voids of multi-chip package.|본 논문에서는 다중 칩 패키지 검사를 위한 테라헤르츠 비파괴 검사 방법을 제시하였다. 테라헤르츠파 검사를 위해 저주파 영역의 테라헤르츠 광원을 사용하면서도 고해상도의 분해능을 얻기 위한 방법으로 공진형 슬릿 프로브를 적용하였다. 그러나 종래의 공진형 슬릿 구조는 슬릿 두께가 얇아 제작이 어려울 뿐만 아니라 슬릿 두께 오차에 따른 공진주파수 변화 및 반사손실(Return loss)이 증가하는 문제가 발생한다. 테라헤르츠파 영역에서의 슬릿 두께 문제를 개선하면서도 결합 효율을 높이기 위한 방법으로 둥근 정합 구조를 가진 공진형 슬릿 프로브를 제안하였다. 제안 된 프로브는 슬릿 두께의 증가에도 불구하고 높은 결합 효율을 유지함과 동시에 두께 오차에 따른 공진주파수 변화를 감소시킬 수 있다. 또한, 슬릿 프로브를 이용한 이물 검출 시뮬레이션에서 기존의 공진형 슬릿 구조보다 제안된 구조를 이용함으로써 반치폭 (FWHM)을 40% 이상 감소시킬 수 있었다. 제안된 구조를 적용한 공진 주파수가 205 GHz인 프로브를 전기도금 방식으로 제작하였으며, VNA 측정 결과와 CST MWS 시뮬레이션 결과와 비교하였다. 측정 결과로부터 제안 된 프로브가 구조적으로 간단하면서도 높은 결합 효율을 가짐을 확인하였다. 펄스형 테라헤르츠파 시스템을 구성, 반도체 칩의 편광 방향에 따른 투과 특성을 검증하여 테라헤르츠파를 이용한 반도체 검사가 가능함을 확인하였다. 공정 검사 적용이 가능한 연속형 테라헤르츠파 검사 시스템을 구축하였다. 방향성 커플러 (Directional coupler) 기반의 테라헤르츠파 송수신기 모듈과 매직 티 (Magic-tee) 기반의 테라헤르츠파 송수신기 모듈을 구성하였다. 또한, 공정 검사를 위한 검출 속도를 개선하기 위해 FPGA 기반의 고속 락인앰프 (lock-in amplifier)가 제작되었으며 반도체 표면의 도전성을 고려한 표준 샘플을 제작하여 측정 시스템과 프로브의 성능 검증을 위해 사용되었습니다. 매직 티 기반의 테라헤르츠파 트랜시버 모듈이 결함 검출에 더 적합함을 확인하였으며, 시스템을 이용한 프로브의 공간 분해능 검증 결과 100 µm의 공간 해상도을 가졌다. 또한, 고속 신호 처리 모듈을 이용하여 1000mm/s의 고속 이동 중에도 안정적으로 영상 검출이 가능함을 확인하였다. 반도체 칩을 이용한 검사에서는 반도체 표면의 높은 도전성으로 반사형 테라헤르츠파 시스템으로는 Void 검출이 어려워 측 방향(lateral) 검사 방식을 제안하였다. CST Microwave Studio 시뮬레이션을 통하여 측 방향 검사로 보이드 (Void) 검출이 가능함을 확인하였다. 측 방향 검사 시스템을 구성하였으며 적층 반도체 내의 직경 500 ㎛의 보이드를 검출하였다. 또한, 검출 영상에 간단한 콘트라스트 스트레칭 변환 영상 필터를 적용하여 프로브 구조에 따른 검출 신호를 개선함으로써 적층 구조 내의 결함을 쉽게 판별이 가능하도록 하였다. 결과적으로 제안된 프로브를 적용한 테라헤르츠파 시스템이 적층 반도체 내의 Void 검출을 위한 새로운 검사 방법임을 확인하였다.1. Introduction 1 1.1 Motivation 1 1.2 Outline 3 2. Background 5 2.1 Multi-chip package inspection technology and their Limit 5 2.1.1 Multi-chip package inspection using ultrasound 5 2.1.2 Multi-chip package inspection using infra-Red (IR) 6 2.1.3 Multi-chip package inspection using X-ray 8 2.2 THz inspection technology 9 2.2.1 Advantages of THz inspection technology 9 2.2.2 Issues in the THz inspection technology 12 2.2.3 THz technology for multi-chip package inspection 16 3. Resonant slit-type probe 19 3.1 Design of a resonant slit-type probe 19 3.1.1 Advantages of resonant slit-type probe 19 3.1.2 Theory of resonant slit-type probe 20 3.1.3 Resonant slit-type probe for THz wave 23 3.1.4 Matching structure of resonant slit-type probe 27 3.2 Resonant slit-type probe with rounded matching structure 27 3.2.1 Resonant slit-type probe with rounded matching structure 27 3.2.2 Fabrication of slit-type probe with rounded matching structure 34 3.2.3 Measurement of slit-type probe with rounded matching structure 37 4. Experimental setup 39 4.1 Components for CW THz imaging system 40 4.1.1 CW THz source 40 4.1.2 CW THz detector 41 4.1.3 FPGA based on fast lock-in amplifier 41 4.1.4 Fabrication of standard sample 48 4.2 CW THz Transceiver module for multi-chip package inspection 51 4.2.1 Design of THz transceiver module 51 4.2.2 Magic-tee based THz transceiver 56 4.2.3 Directional coupler based THz transceiver 56 5. Measurements and results 59 5.1 Verification of performance of THz imaging system 59 5.1.1 Measurement of spatial resolution of resonant slit-type probe with rounded matching structure 59 5.1.2 High-speed signal processing and image acquisition 60 5.2 Semiconductor chip inspection using pulsed THz wave 65 5.2.1 Inspection system using pulsed THz wave 65 5.2.2 Semiconductor chip inspection using pulsed THz wave 67 5.2.3 Transmission characteristics according to the polarization 72 5.3 Semiconductor chip inspection using CW THz wave 73 5.3.1 Semiconductor chip inspection using CW THz system based on directional Coupler 77 5.3.2 Semiconductor chip inspection using CW THz system based on magic-tee 80 5.3.3 Semiconductor chip inspection using CW THz wave 83 5.4 Multi-chip package inspection using CW THz wave 83 5.4.1 THz propagation in voids of multi-chip package in lateral inspection 83 5.4.2 Multi-chip package inspection using lateral inspection methode 85 5.4.3 Improvement of void image using image processing technique 89 5.4.4 Another application using slit-type probe (Food inspection) 93 6. Conclusion 99 Reference 103Docto

Waveguide-based antenna arrays in multi-chip module technology

For mm-waves, two types of low-loss waveguide are analysed, designed and measured. One is the hollow substrate integrated waveguide (HSIW) in which the inner dielectric of a traditional substrate integrated waveguide (SIW) is removed to resemble the propagation characteristics of a standard rectangular waveguide (RWG). The measured attenuation of a WR28-like HSIW is 2 Np/m or 17 dB/m throughout the Ka band. The second is the dielectric insular image guide (DIIG) in which an insular layer is added between the dielectric and the metallic ground to further reduce the conductor loss. The measured attenuation of a Ka band DIIG is 26 dB/m at 35 GHz. Based on the two waveguides, two high-gain antenna arrays operating in the Ka band are designed and measured. One is a 6 x 6 slot antenna array, centrefed by the HSIW. The Taylor-distribution technique is applied in two orthogonal directions to suppress the sidelobe level. The measured gain of this antenna array is 17.1 dBi at the centre frequency of 35.5 GHz. The other is a double-sided 10- element dielectric insular resonator antenna (DIRA) array, end-fed by the DIIG. The Taylor-distribution technique is also applied here to achieve a gain of 15.8 dBi at the centre frequency of 36 GHz. The great potential of these high-performance antennas is that they can be integrated with other microwave components (filters, power amplifiers, etc.) to form a complete front-end or transceiver in multi-chip module (MCM) technology

Co-Package Technology Platform for Low-Power and Low-Cost Data Centers

We report recent advances in photonic–electronic integration developed in the European research project L3MATRIX. The aim of the project was to demonstrate the basic building blocks of a co-packaged optical system. Two-dimensional silicon photonics arrays with 64 modulators were fabricated. Novel modulation schemes based on slow light modulation were developed to assist in achieving an efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Improved semiconductor quantum dot MBE growth, characterization and gain stack designs were developed. Packaging of these 2D photonic arrays in a chiplet configuration was demonstrated using a vertical integration approach in which the optical interconnect matrix was flip-chip assembled on top of a CMOS mimic chip with 2D vertical fiber coupling. The optical chiplet was further assembled on a substrate to facilitate integration with the multi-chip module of the co-packaged system with a switch surrounded by several such optical chiplets. We summarize the features of the L3MATRIX co-package technology platform and its holistic toolbox of technologies to address the next generation of computing challenges

Minimalistic SDHC-SPI hardware reader module for boot loader applications

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software boot loader and the related memory resources. The hardware overhead introduced is manageable, even in low-range FPGA chips, and negligible in mid- and high-range devices. The implementation of the SD card reader module is explained in detail and an example of a multi-boot loader is offered as well. The multi-boot loader is implemented and tested with the Xilinx's Picoblaze microcontroller

A Manufacturer Design Kit for Multi-Chip Power Module Layout Synthesis

The development of Multi-Chip Power Modules (MCPMs) has been a key factor in recent advancements in power electronics technologies. MCPMs achieve higher power density by combining multiple power semiconductor devices into one package. The work detailed in this thesis is part of an ongoing project to develop a computer-aided design software tool known as PowerSynth for MCPM layout synthesis and optimization. This thesis focuses on the definition and design of a Manufacturer Design Kit (MDK) for PowerSynth, which enables the designer to design an MCPM for a manufacturer’s fabrication process. The MDK is comprised of a layer stack and technology library, design rule checking (DRC), and layout versus schematic checking. File formats have been defined for layer stack and design rule input, and import functions have been written and integrated with the existing user interface and data structures to allow PowerSynth to accept these file formats as a form of input. Finally, an exhaustive DRC function has been implemented to allow the designer to verify that a synthesized layout meets all design rules before committing the design to manufacturing. This function was validated by running DRC on an example layout solution using two different sets of design rules