The RD53 collaboration is currently designing a large scale prototype pixel
readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC.
The RD53A chip will be available by the end of the year 2017 and will be
extensively tested to confirm if the circuit and the architecture make a solid
foundation for the final pixel readout chips for the experiments at the HL-LHC.
A test and data acquisition system for the RD53A chip is currently under
development to perform single-chip and multi-chip module measurements. In
addition, the verification of the RD53A design is performed in a dedicated
simulation environment. The concept and the implementation of the test and data
acquisition system and the simulation environment, which are based on a modular
data acquisition and system testing framework, are presented in this work