Design of reconfigurable multi-mode RF circuits

Wireless communication systems and devices have been developing at a much faster pace in the past few years. With the introduction of new applications and services and the increasing demand for higher data rate comes the need for new frequency bands and new standards. One critical issue for next generation wireless devices is how to support all of the existing and emerging bands while not increasing the cost and power consumption. A feasible solution is the concept of the software-defined radio where a single receiver can be reconfigured to operate in different modes, each of which supports one or several bands and/or standards. To implement such a reconfigurable receiver, reconfigurable RF building blocks, such as the LNA, mixer, VCO, etc., are required. This dissertation focuses on two key blocks: the low noise amplifier (LNA) and the voltage controlled oscillator (VCO). First the design, modeling and characterization of a multi-tap transformer are discussed. Simple mathematical calculations are utilized to estimate the inductances and coupling coefficients from the physical parameters of a multi-tap transformer. The design method is verified with several designed multi-tap transformers that are characterized up to 10 GHz using Momentum simulation results. The effect of switch loss on a switched multi-tap transformer is explored and a broadband lumped-element model of the multi-tap transformer is also proposed. Next a reconfigurable multimode LNA capable of single-band, concurrent dual-band, and ultra-wideband operation is presented. The multimode operation is realized by incorporating a switched multi-tap transformer into the input matching network of an inductively degenerated common source amplifier. The proposed LNA achieves single band matching at 2.8, 3.3, and 4.6 GHz; concurrent dual-band matching at 2.05 and 5.65 GHz; and ultra-wideband matching from 4.3 to 10.8 GHz. The chip was fabricated in a 0.13 m CMOS process, and occupies an area of 0.72 mm2, and has a power dissipation of 6.4 mW from a 1.2-V supply. Finally, a triple-mode VCO using a transformer-based 4th order tank with tunable transconductance cells coupling the primary and secondary inductor is introduced. The tank impedance can be re-shaped by the transconductance cells through the tuning of their biasing currents. With the control of biasing current, VCO is configured in three modes, capable of generating a single frequency in 3- and 5- GHz bands, respectively, and two frequencies in both 3- and 5- GHz bands simultaneously. The triple-mode VCO was fabricated in a 0.13 μm CMOS process, occupies an area of 0.16 mm2, and dissipates 5.6 mW from a 1.2-V supply

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

고효율 고전압 포락선 추적 전력 증폭기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 서광석.In this dissertation, two advanced techniques to solve system issues in envelope tracking power amplifier (ET PA) is presented. First of all, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realizedwith a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32-μm silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratios (ACLRs) are better than –33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS. Second, a high-efficiency gallium-nitride (GaN) envelope amplifier (EA) is developed using class-E2 architecture for wideband LTE applications. The proposed EA consists of a class-E2 resonant converter which output voltage is controlled by a frequency modulator. With a pulse frequency modulation (PFM) signal, the output of the converter can achieve a linear response to the input wideband envelope signal. The frequency modulator with a cross-coupled oscillator and a driver using stacked-FETs structure is fabricated using 0.28-μm SOI CMOS process. The class-E2 converter and PA have been implemented using a commercial GaN device. The envelope amplifier (EA) achieves 74.7% efficiency into a 50 Ω load for a 20-MHz BW LTE signal with a 7.5 dB peak-to-average power ratio (PAPR) and there is no efficiency degradation as the LTE signal bandwidth increases to 160-MHz. The ET transmitter system demonstrated using the CMOS and GaN shows an overall system efficiency of 47.4% at 35.4 dBm with 20-MHz BW LTE signal centered at 3.5 GHz. The measured E-UTRA ACLR of ET PA is –33.8 dBc at 34.4 dBm output power before linearization and –42.9 dBc at the same output power after memory digital pre-destination (DPD). When tested using 80-MHz BW LTE signal, the overall system PAE reaches 46.5% at 35.3 dBm output power and E-UTRA ACLR was measured by –31.5 dBc at 34.4 dBm output power. A wideband performance is characterized using various bandwidth LTE signals which shows only 2.3 dB ACLR degradation without PAE degradation as the signal bandwidth is increased from 20- to 80-MHz. The proposed method is a first demonstration of GaN EA cover 160-MHz BW LTE signals and overcomes the efficiency degradation of the conventional EA as the signal bandwidth increase.Abstract Contents List of Tables List of Figures 1. Introduction 1.1 Motivation 1.2 Dissertation organization 2. Broadband CMOS Stacked RF Power Amplifier Using Reconfigurable Interstage Network for Wideband Envelope Tracking 2.1 Introduction 2.2 Two-stage broadband class-J PA 2.2.1 Review of the class-J PA 2.2.2 BW limitation in multi-stage PAs and proposed solution 2.2.3 Output matching netwok 2.2.4 Reconfigurable interstage matching network 2.3 Design and implementation of ET PA 2.3.1 Power amplifier design 2.3.2 Envelope amplifier design 2.4 Measurement results 2.5 Conclusions 2.6 References 3. A GaN Envelope Amplifier using Class-E2 Architecture for Wideband Envelope Tracking Applications 3.1 Introduction 3.2 Operation principle of the proposed envelope amplifier 3.2.1 Operation principle of class-E inverter and rectifier 3.2.2 Operation comparison of class-E2 between PWM and PFM 3.3 Detailed ET PA design and simulation 3.3.1 Envelope amplifier design using current-starved VCO (CSVCO) 3.3.2 Envelope amplifier design using cross-coupled VCO (CCVCO) 3.4 Measurement results 3.5 Conclusions 3.6 References 4. Conclusions and Future Works Abstract in KoreanDocto

Realization of analog signal processing modules using carbon nanotube field effect transistors

This thesis presents the realization and performance analysis of several carbon nanotube field effect transistor (CNTFET) based analog signal processing (ASP) modules. CNTFET is predicted as a possible successor to conventional silicon complementary metal oxide semiconductor (CMOS), which has reached its scaling limits. The CMOS based ASP modules face significant challenges at deep nanoscale, resulting in severe performance degradations due to short channel effects. The main goal of this work is to realize CNTFET active building blocks (ABBs), and then to utilize these ABBs for realization of low-voltage, low-power, and high-frequency ASP modules. The proposed ABBs have low power dissipation, reduced parasitic components, and minimum number of CNTFETs. The proposed modules are active inductor (AI), first-order phase shifter, and second-order phase shifter. This research proposes a new CNTFET based grounded AI (GAI) circuit with high self-resonance frequency (SRF), wide tunable inductance range, and high quality factor. Simulation results demonstrate that the GAI offers tunable inductance from 4.4 nH to 287.4 nH with a maximum SRF of 101 GHz. It consumes very low power dissipation of 0.337 mW. In comparison to high performance available GAI circuits, the proposed GAI shows 34% reduction in power dissipation and nine times higher SRF. A highfrequency low-noise amplifier (LNA) circuit is also designed by utilizing the proposed GAI to showcase its application. The simulation result shows high frequency bandwidth of 17.5 GHz to 57 GHz, 15.9 dB maximum voltage gain, better than -10 dB input matching, and less than 3 dB noise figure. This research also proposes a compact wideband first-order phase shifter (FOPS) and active-only FOPS (AOFOPS). Simulation results demonstrate the FOPS has a tunable pole frequency range between 1.913 GHz and 40.2 GHz, input and output voltage noises of 4.402 nV/VHz and 4.414 nV/VH z respectively, and power dissipation of 0.4862 mW. The AOFOPS circuit also offers a wide tunable range of pole frequency between 34.2 GHz to 56.4 GHz with input noise and output noise of 6.822 nV/VHz and 6.761 nV/VHz respectively, and power dissipation of only 0.0338 mW. The AOFOPS dissipates 12.40 times less power in comparison to state-of-art FOPS circuits. This work also proposes active-only second-order phase shifter. The proposed circuit provides a tunable pole frequency between 16.2 GHz to 42.5 GHz, with input and output noises of 21.698 nV/VHz and 21.593 nV/VHz respectively, while consuming 0.2256 mW power. All circuit performances are verified through HSPICE simulation by utilizing the Stanford CNTFET model at 16 nm technology node with supply voltage of 0.7 V

Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz

準ミリ波・ミリ波領域における低位相雑音電圧制御発振器のLC共振器に関する研究

2017岡山県立大学大学

A Low Phase Noise Wide-Tuning Range Class-F VCO Based on a Dual-Mode Resonator in 65nm CMOS

A Voltage Controlled Oscillator (VCO) is a critical building block in the design of current frequency synthesizers for RF system applications. State-of-the-art operation defines that an oscillator should have the best spectral purity while consuming low amount of power for a wide tuning range. With this in mind, this work presents a low phase noise wide tuning range ClassF VCO using a dual-mode resonator. In comparison to other conventional wideband oscillators, the proposed capacitively/inductively-coupled resonator will integrate the benefits of Class-F voltage control oscillators and dual-mode switching networks to obtain simultaneous low phase noise and wide-tuning range. The proposed structure, prototyped in 65nm TSMC CMOS technology, shows a 2.14 – 4.22GHz continuous tuning range, phase noise figure-of-merit (FoM) of 192.7dB at 2.3GHz and better than 188dB across the entire operating frequency range. The oscillator consumes 15-16.4mW from a 0.6V supply and occupies an active area of 0.7mm^2 . In conclusion, the proposed resonator achieves 2- 3dB phase noise improvement while achieving 65% overall tuning range when compared to a typical class-F VCO architecture