Physical Modeling of Graphene Nanoribbon Field Effect Transistor Using Non-Equilibrium Green Function Approach for Integrated Circuit Design

The driving engine for the exponential growth of digital information processing systems is scaling down the transistor dimensions. For decades, this has enhanced the device performance and density. However, the International Technology Roadmap for Semiconductors (ITRS) states the end of Moore’s law in the next decade due to the scaling challenges of silicon-based CMOS electronics, e.g. extremely high power density. The forward-looking solutions are the utilization of emerging materials and devices for integrated circuits. The Ph.D. dissertation focuses on graphene, one atomic layer of carbon sheet, experimentally discovered in 2004. Since fabrication technology of emerging materials is still in early stages, transistor modeling has been playing an important role for evaluating futuristic graphene-based devices and circuits. The GNR FET has been simulated by solving a numerical quantum transport model based on self-consistent solution of the 3D Poisson equation and 1D Schrödinger equations within the non-equilibrium Green’s function (NEGF) formalism. The quantum transport model fully treats short channel-length electrostatic effects and the quantum tunneling effects, leading to the technology exploration of graphene nanoribbon field effect transistors (GNRFETs) for the future. A comprehensive study of static metrics and switching attributes of GNRFET has been presented including the performance dependence of device characteristics to the GNR width and the scaling of its channel length down to 2.5 nanometer. It has been found that increasing the GNR width deteriorate the off-state performance of the GNRFET, such that, narrower armchair GNRs improved the device robustness to short channel effects, leading to better off-state performance considering smaller off-current, larger ION/IOFF ratio, smaller subthreshold swing and smaller drain-induced barrier-lowering. The wider armchair GNRs allow the scaling of channel length and supply voltage resulting in better on-state performance such as higher drive current, smaller intrinsic gate-delay time and smaller power-delay product. In addition, the width-dependent characteristics of GNR FETs is investigated for two GNR semiconducting families (3p,0) and (3p+1,0). It has been found that the GNRs(3p+1,0) demonstrates superior off-state performance, while, on the other hand, GNRs(3p,0) shows superior on-state performance. Thus, GNRs(3p+1,0) are promising for low-power design, while GNRs(3p,0) indicate a more preferable attribute for high frequency applications

Demonstration of monolithically integrated graphene interconnects for low-power CMOS applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 129-141).In recent years, interconnects have become an increasingly difficult design challenge as their relative performance has not improved at the same pace with transistor scaling. The specifications for complex features, clock frequency, supply current, and number of I/O resources have added even greater demands for interconnect performance. Furthermore, the resistivity of copper begins to degrade at smaller line widths due to increased scattering effects. Graphene has gathered much interest as an interconnect material due to its high mobility, high current carrying capacity, and high thermal conductivity. DC characterization of sub-50 nm graphene interconnects has been reported but very few studies exist on evaluating their performance when integrated with CMOS. Integrating graphene with CMOS is a critical step in establishing a path for graphene electronics. In this thesis, we characterize the performance of integrated graphene interconnects and demonstrate two prototype CMOS chips. A 0.35 prm CMOS chip implements an array of transmitter/receivers to analyze end-to-end data communication on graphene wires. Graphene sheets are synthesized by chemical vapor deposition, which are then subsequently transferred and patterned into narrow wires up to 1 mm in length. A low-swing signaling technique is applied, which results in a transmitter energy of 0.3-0.7 pJ/bit/mm, and a total energy of 2.4-5.2 pJ/bit/mm. We demonstrate a minimum voltage swing of 100 mV and bit error rates below 2x10-10. Despite the high sheet resistivity of graphene, integrated graphene links run at speeds up to 50 Mbps. Finally, a subthreshold FPGA was implemented in 0.18 pm CMOS. We demonstrate reliable signal routing on 4-layer graphene wires which replaces parts of the interconnect fabric. The FPGA test chip includes a 5x5 logic array and a TDC-based tester to monitor the delay of graphene wires. The graphene wires have 2.8x lower capacitance than the reference metal wires, resulting in up to 2.11x faster speeds and 1.54x lower interconnect energy when driven by a low-swing voltage of 0.4 V. This work presents the first graphene-based system application and demonstrates the potential of using low capacitance graphene wires for ultra-low power electronics.by Kyeong-Jae Lee.Ph.D

Two-Dimensional Electronic Materials and Devices: Opportunities and Challenges

The unprecedented growth of the Internet of Things (IoT) and the 4th Industrial Revolution (Industry 4.0) not only demands dimensional scaling of device technologies but also new types of applications beyond today’s electronics. Two-dimensional (2D) materials, a group of layered crystals (such as graphene and MoS2) with unique properties, have emerged as promising candidates for IoT and Industry 4.0 since they can, not only extend the scaling with unprecedented performance and energy efficiency but also exhibit high potential for novel electronic devices. However, such nanomaterials suffer from significant challenges in process integration, especially in the modules that involves the formation of interfaces between 2D materials and conventional bulk materials. Thus, realizing high-performance energy-efficient 2D electronic devices has been challenging. This dissertation focuses on understanding the fundamental issues in such 2D materials (such as contacts, interfaces and doping) and in identifying applications uniquely enabled by these materials.First, a comprehensive treatment of metal contacts to 2D semiconductors, which has been a huge hurdle for 2D electronic technologies, will be presented. As a pioneering study, new interface physics originating from the unique dimensionality and surface properties have been revealed [1]. Solutions to minimize contact resistance are described though techniques of interface hybridization [2] and seamless contacts [3], [4]. These techniques transform 2D semiconductors from solely scientifically-interesting materials into high-performance field-effect transistor (FET) technologies, such as MoS2 FETs with record-low contact resistances [5], [6] and WSe2 FETs with record-high drive current and mobility [7]. Beyond metal interfaces, dielectric interface is crucial for preserving the carrier mobility in 2D channels, for which a solution enabled by buffer layers has been proposed [8]. On the other hand, the vertical van der Waals interfaces between 2D and 3D semiconductors, which retain the advantages of pristine ultra-thin 2D films as well as maximized tunneling area/field, have been studied and exploited into a novel beyond-silicon transistor technology – the first 2D channel tunnel FET (TFET) [9], which beat the fundamental limitation in the switching behavior of transistors. Recent results from the engineering of such 2D-3D semiconductor interfaces by surface reduction/passivation are described, showing a significant boost of drive current. While conventional diffusion/ion implantation methods are infeasible for 2D materials, two efficient doping techniques that are specific for 2D materials – surface doping [10], [11] and intercalation doping [12] are presented. The theoretical study of surface doping using ab-initio methods helped develop a novel doping scheme that uniquely exploits the Lewis-base like pedigree of 2D semiconductors without disturbing the structural integrity of the 2D atomic layer configuration [13], as well as a novel electrocatalyst based on MoS2 that achieved record high hydrogen evolution reaction (HER) performance [14]. On the other hand, intercalation doping has been employed to demonstrate graphene based transparent electrodes with the best combination of transmittance and sheet resistance [12], and also the first graphene interconnects with excellent performance, reliability and energy-efficiency [15], [16]. Moreover, by uniquely exploiting the high kinetic inductance and conductivity of intercalation doped graphene, a fundamentally different on-chip inductor has been demonstrated [17], [18], with both small form-factors and high inductance values, that were once thought unachievable in tandem. This 2D technique provides an attractive solution to the longstanding scaling problem of analog/radio-frequency electronics and opens up an unconventional pathway for the development of future ultra-compact wireless communication systems. Finally, a novel dissipative quantum transport methodology based on Büttiker probes with band-to-band tunneling capability is developed for 2D FETs [19]. Subsequently, gate-induced-drain-leakage (GIDL), one of the main leakage mechanisms in FETs especially access transistors, is evaluated for the first time for 2D FETs. The results establish the advantages of certain 2D semiconductors in greatly reducing GIDL and thereby support use of such materials in future memory technologies.The dissertation concludes with a vision for how a smart life can be realized in the future by harnessing the capabilities of various 2D technologies in the era of IoT and Industry 4.0.[1] J. Kang, D. Sarkar, W. Liu, D. Jena, and K. Banerjee, “A computational study of metal-contacts to beyond-graphene 2D semiconductor materials,” in IEEE International Electron Devices Meeting, 2012, pp. 407–410.[2] J. Kang, W. Liu, D. Sarkar, D. Jena, and K. Banerjee, “Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors,” Phys. Rev. X, vol. 4, no. 3, p. 31005, Jul. 2014.[3] J. Kang, D. Sarkar, Y. Khatami, and K. Banerjee, “Proposal for all-graphene monolithic logic circuits,” Appl. Phys. Lett., vol. 103, no. 8, p. 83113, 2013.[4] A. Allain, J. Kang, K. Banerjee, and A. Kis, “Electrical contacts to two-dimensional semiconductors,” Nat. Mater., vol. 14, no. 12, pp. 1195–1205, 2015.[5] W. Liu et al., “High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance,” in IEEE International Electron Devices Meeting, 2013, pp. 499–502.[6] J. Kang, W. Liu, and K. Banerjee, “High-performance MoS2 transistors with low-resistance molybdenum contacts,” Appl. Phys. Lett., vol. 104, no. 9, p. 93106, Mar. 2014.[7] W. Liu, J. Kang, D. Sarkar, Y. Khatami, D. Jena, and K. Banerjee, “Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors.,” Nano Lett., vol. 13, no. 5, pp. 1983–90, May 2013.[8] J. Kang, W. Liu, and K. Banerjee, “Computational Study of Interfaces between 2D MoS2 and Surroundings,” in 45th IEEE Semiconductor Interface Specialists Conference, 2014.[9] D. Sarkar et al., “A subthermionic tunnel field-effect transistor with an atomically thin channel,” Nature, vol. 526, no. 7571, pp. 91–95, Sep. 2015.[10] Y. Khatami, W. Liu, J. Kang, and K. Banerjee, “Prospects of graphene electrodes in photovoltaics,” in Proceedings of SPIE, 2013, vol. 8824, p. 88240T–88240T–6.[11] D. Sarkar et al., “Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing,” Nano Lett., vol. 15, no. 5, pp. 2852–2862, May 2015.[12] W. Liu, J. Kang, and K. Banerjee, “Characterization of FeCl3 intercalation doped CVD few-layer graphene,” IEEE Electron Device Lett., vol. 37, no. 9, pp. 1246–1249, Sep. 2016.[13] S. Lei et al., “Surface functionalization of two-dimensional metal chalcogenides by Lewis acid–base chemistry,” Nat. Nanotechnol., vol. 11, no. 5, pp. 465–471, Feb. 2016.[14] J. Li, J. Kang, Q. Cai, W. Hong, C. Jian, and W. Liu, “Boosting Hydrogen Evolution Performance of MoS2 by Band Structure Engineering,” Adv. Mater. Interfaces, vol. 1700303, 2017.[15] J. Jiang et al., “Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects,” Nano Lett., vol. 17, no. 3, pp. 1482–1488, Mar. 2017.[16] J. Jiang, J. Kang, and K. Banerjee, “Characterization of Self - Heating and Current - Carrying Capacity of Intercalation Doped Graphene - Nanoribbon Interconnects,” in IEEE International Reliability Physics Symposium, 2017, p. 6B.1.1-6B.1.6.[17] X. Li et al., “Graphene inductors for high-frequency applications - design, fabrication, characterization, and study of skin effect,” in IEEE International Electron Devices Meeting, 2014, p. 5.4.1-5.4.4.[18] J. Kang et al., under review.[19] J. Kang et al., under review

Modeling Of Two Dimensional Graphene And Non-graphene Material Based Tunnel Field Effect Transistors For Integrated Circuit Design

The Moore’s law of scaling of metal oxide semiconductor field effect transistor (MOSFET) had been a driving force toward the unprecedented advancement in development of integrated circuit over the last five decades. As the technology scales down to 7 nm node and below following the Moore’s law, conventional MOSFETs are becoming more vulnerable to extremely high off-state leakage current exhibiting a tremendous amount of standby power dissipation. Moreover, the fundamental physical limit of MOSFET of 60 mV/decade subthreshold slope exacerbates the situation further requiring current transport mechanism other than drift and diffusion for the operation of transistors. One way to limit such unrestrained amount of power dissipation is to explore novel materials with superior thermal and electrical properties compared to traditional bulk materials. On the other hand, energy efficient steep subthreshold slope devices are the other possible alternatives to conventional MOSFET based on emerging novel materials. This dissertation addresses the potential of both advanced materials and devices for development of next generation energy efficient integrated circuits. Among the different steep subthreshold slope devices, tunnel field effect transistor (TFET) has been considered as a promising candidate after MOSFET. A superior gate control on source-channel band-to-band tunneling providing subthreshold slopes well below than 60 mV/decade. With the emergence of atomically thin two-dimensional (2D) materials, interest in the design of TFET based on such novel 2D materials has also grown significantly. Graphene being the first and the most studied among 2D materials with exotic electronic and thermal properties. This dissertation primarily considers current transport modeling of graphene based tunnel devices from transport phenomena to energy efficient integrated circuit design. Three current transport models: semi-classical, semi-quantum and numerical simulations are described for the modeling of graphene nanoribbon tunnel field effect transistor (GNR TFET) where the semi-classical model is in close agreement with the quantum transport simulation. Moreover, the models produced are also extended for integrated circuit design using Verilog-A hardware description language for logic design. In order to overcome the challenges associated with the band gap engineering for making graphene transistor for logic operation, the promise of graphene based interlayer tunneling transistors are discussed along with their existing fundamental physical limitation of subthreshold slope. It has been found that such interlayer tunnel transistor has very poor electrostatic gate control on drain current. It gives subthreshold slope greater than the thermionic limit of 60 mV/decade at room temperature. In order to resolve such limitation of interlayer tunneling transistors, a new type of transistor named “junctionless tunnel effect transistor (JTET)” has been invented and modeled for the first time considering graphene-boron nitride (BN)-graphene and molybdenum disulfide (MoS2)-boron nitride (BN) heterostructures, where the interlayer tunneling mechanism controls the source-drain ballistic transport instead of depleting carriers in the channel. Steep subthreshold slope, low power and high frequency THz operation are few of the promising features studied for such graphene and MoS2 JTETs. From current transport modeling to energy efficient integrated circuit design using Verilog-A has been carried out for these new devices as well. Thus, findings in this dissertation would suggest the exciting opportunity of a new class of next generation energy efficient material based transistors as switches

Impact of materials disorder on graphene heterostructure devices

This work is focused on characterizing the impact of material based disorder on the properties of graphene based vertical tunneling heterostructures. The motivation and challenges for replacing silicon for low power digital electronics has been presented. The status of the research on graphene based digital electronics is critically reviewed. Scalable methods for synthesizing large area two dimensional materials including graphene, molybdenum disulfide, and hexagonal boron nitride are integrated into a complex CMOS fabrication process to investigate the impact of disorder on the properties of vertical graphene based heterostructures for low power digital electronics. The CMOS fabrication process was found to introduce contaminants in the form of polymeric residues that reduced the lateral conduction of the graphene. Thermal decomposition of the residues resulted in the introduction of defects in the graphene. A chemical etching method utilizing a sacrificial titanium layer removed via HF etching effectively removed the contaminants without damaging the graphene. Dielectric tunneling barriers were deposited by atomic layer deposition (ALD). The composition of the tunneling barrier was experimentally shown to alter the electrical performance of the graphene heterostructure and allows barrier engineering for tailoring the electrical properties of the device. The thickness of the tunneling barrier was shown to control the dominant tunneling mechanism with barriers less than ~3 nm required for direct tunneling. The impact of the graphene on the electrical performance of the device was investigated by using graphene of various domain sizes. No dependence was found on the graphene domain size suggesting the tunneling barrier dielectric or device substrate is limiting the device performance. Following recent reports utilizing exfoliated materials, two dimensional materials (molybdenum disulfide and hexagonal boron nitride) complimentary to graphene were utilized as tunneling dielectrics to further improve the device performance over conventional dielectric materials. The direct synthesis of complimentary two dimensional materials on graphene was shown to introduce defects into the graphene structure and to suppress the electrical properties of the device. Trapping of electrons in the MoS2 defect states was shown to drastically suppress the tunneling current compared to less defective exfoliated materials. Decreasing the synthesis temperature of the MoS2 was shown as a potential pathway for reducing the induced defects in the graphene. A large area synthesized hexagonal boron nitride buffer layer was shown to improve the lateral conduction of the graphene. Contrary to reports of exfoliated materials, the introduction of a hexagonal boron nitride tunneling barrier was shown to reduce the mobility of the graphene due to increased scattering as a result of defects in the hexagonal boron nitride as well as contamination introduced during the transfer process. The lateral conductance of the graphene was shown to be improved in the graphene vertical heterostructure with a hexagonal boron nitride buffer layer, but was insufficient to improve the overall device performance. Improved synthesis methods to reduce the intrinsic defects in the as synthesized hexagonal boron nitride is necessary to further improve the graphene heterostructure performance.Ph.D

Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes

Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior currentcarrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm 40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge

Two-Dimensional Electronics - Prospects and Challenges

During the past 10 years, two-dimensional materials have found incredible attention in the scientific community. The first two-dimensional material studied in detail was graphene, and many groups explored its potential for electronic applications. Meanwhile, researchers have extended their work to two-dimensional materials beyond graphene. At present, several hundred of these materials are known and part of them is considered to be useful for electronic applications. Rapid progress has been made in research concerning two-dimensional electronics, and a variety of transistors of different two-dimensional materials, including graphene, transition metal dichalcogenides, e.g., MoS2 and WS2, and phosphorene, have been reported. Other areas where two-dimensional materials are considered promising are sensors, transparent electrodes, or displays, to name just a few. This Special Issue of Electronics is devoted to all aspects of two-dimensional materials for electronic applications, including material preparation and analysis, device fabrication and characterization, device physics, modeling and simulation, and circuits. The devices of interest include, but are not limited to transistors (both field-effect transistors and alternative transistor concepts), sensors, optoelectronics devices, MEMS and NEMS, and displays

Graphene Nanoelectronics - From Synthesis to Device Applications.

Nanotechnology is the pinnacle of the scientific effort to breach the dimensional limit in matter. Every now and then, this technology offers us a rare glimpse into the true potential of a common material. Graphite, a material found in pencils, has been used by humans since the 4th millennium BC. When atomic particles in graphite are confined in the two-dimensional nanoscale limit, these quasiparticles enter an exclusive domain of relativistic electron theory of the Dirac equation. This single atomic sheet of carbon atoms that provides the confinement is called graphene. In this thesis, we present research efforts to harness the extraordinary attributes of graphene and explore new possibilities in the field of nanoelectronics. First, the importance of bilayer graphene and its tunable bandgap is discussed. For the first time, a rational route to synthesize wafer scale bilayer graphene is investigated using a low-pressure chemical vapor deposition (LPCVD) method. Subsequently, the existence of tunable bandgap devices are confirmed with cryogenic carrier transport measurements from dual-gate bilayer graphene transistors. We further explore the feasibility of a bilayer graphene-based, flexible, transparent conductor, and confirm the efficiency and the exceptional mechanical robustness of the material. Next, we report flexible and transparent all-graphene circuits for binary and quaternary digital modulations for the first time. Importantly, the entire modulator circuits are fabricated with graphene only, and this monolithic structure allows unprecedented mechanical flexibility and near-complete transparency. By exploiting the ambipolarity and the nonlinearity in graphene transistors, we achieved quadrature phase shift keying (QPSK) using just two graphene transistors, representing a drastic reduction in circuit complexity when compared with conventional silicon-based modulators. Lastly, we address the shortcomings of small gain in conventional graphene transistors by designing the very first graphene heterostructure bipolar junction transistor. The exploitation of graphene's low density of states and tunable Fermi level leads to graphene-semiconductor junctions with higher emitter injection efficiency compared to that of a conventional Schottky junction. This property is utilized for the invention of a graphene-based bipolar junction transistor with high on/off ratio(>100,000) and current gain (>33).PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98039/1/seansl_1.pd

Layer by layer printing of nanomaterials for large-area, flexible electronics

Large-area electronics, including printable and flexible electronics, is an emerging concept which aims to develop electronic components in a cheaper and faster manner, especially on those non-conventional substrates. Being flexible and deformable, this new form of electronics is regarded to hold great promises for various futuristic applications including the internet of things, virtual reality, healthcare monitoring, prosthetics and robotics. However, at present, large-area electronics is still nowhere near the commercialisation stage, which is due to several problems associated with performance, uniformity and reliability, etc. Moreover, although the device’s density is not the major concern in printed electronics, there is still a merit in further increasing the total number of devices in a limited area, in order to achieve more electronic blocks, higher performance and multiple functionalities. In this context, this Ph.D. thesis focuses on the printing of various nanomaterials for the realisation of high-performance, flexible and large-area electronics. Several aspects have been covered in this thesis, including the printing dynamics of quasi-1D NWs, the contact problem in device realisation and the strategy to achieve sequential integration (3D integration) of the as-printed devices, both on rigid and flexible substrates. Promisingly, some of the devices based on the printed nanomaterial show a comparable performance to the state-of-the-art technology. With the demonstrated 3D integration strategy, a highly dense array of electronic devices can be potentially achieved by printing method. This thesis also touches on the problem associated with the circuit and system realisation. Specifically, graphene-based logic gates and NW based UV sensing circuit has been discussed, which shows the promising applications of nanomaterial-based electronics. Future work will be focusing on extending the UV sensing circuit to an active matrix sensor array