Reconfigurable Enhanced Path Metric Updater Unit for Space Time Trellis Code Viterbi Decoder

Space Time Trellis Code (STTC) encoding and decoding techniques are effective for delivery of a reliable information because of the signal to noise ratio is very small. Even though the Viterbi algorithm is complicated to be designed, these methods typically used large memory space to store the information that have been processed mainly at the Path Metric Updater (PMU). Therefore, an effective memory management technique is one of the key factors in designing the STTC Viterbi decoder for low power consumption applications. This paper proposed the PMU memory reduction technique especially on Traceback activities that usually required a lot of memories for storing the data that has been processed in the past part by using Altera Quartus 2 and 0.18 µm Altera CPLD 5M570ZF256C5 as targeted hardware. Through this method, the reduction achieved at least 66% of memory requirements and 75% improvements in processing time without a significanct effects on the outputs results of the STTC Viterbi Decoder for 4-PSK modulation technique by using 50MHz clocks

Permutation Trellis Coded Multi-level FSK Signaling to Mitigate Primary User Interference in Cognitive Radio Networks

We employ Permutation Trellis Code (PTC) based multi-level Frequency Shift Keying signaling to mitigate the impact of Primary Users (PUs) on the performance of Secondary Users (SUs) in Cognitive Radio Networks (CRNs). The PUs are assumed to be dynamic in that they appear intermittently and stay active for an unknown duration. Our approach is based on the use of PTC combined with multi-level FSK modulation so that an SU can improve its data rate by increasing its transmission bandwidth while operating at low power and not creating destructive interference for PUs. We evaluate system performance by obtaining an approximation for the actual Bit Error Rate (BER) using properties of the Viterbi decoder and carry out a thorough performance analysis in terms of BER and throughput. The results show that the proposed coded system achieves i) robustness by ensuring that SUs have stable throughput in the presence of heavy PU interference and ii) improved resiliency of SU links to interference in the presence of multiple dynamic PUs.Comment: 30 pages, 12 figure

Design of an Efficient Viterbi Decoder using Xilinx

The vision of wireless communication is to provide high-speed and high-quality exchange of information between two portable devices located anywhere in the world. In this hectic and unsecure world you need to be sure your data is not only safe and secure but that you are working with it at the highest possible speed. Convolutional encoding is a forward error correction technique that is used for correction of errors at the receiver end. The two decoding algorithms used for decoding the convolutional codes are Viterbi algorithm and Sequential algorithm. Sequential decoding has advantage that it can perform very well with long constraint length convolutional codes, but it has a variable decoding time. Viterbi decoding technique is used for decoding the convolutional codes but with the limitation to constraint length. It requires smaller constraint length. The Viterbi algorithm is the most extensively employed decoding algorithm for convolution codes. In digital communication and signal processing the estimation and detection of problems is done by using viterbi algorithm. The Viterbi decoding algorithm is widely used in radio communication, radio relay and satellite communication. This thesis represents the implementation of hard decision Viterbi decoding with constraint length 7 and code rate ½ and its algorithm. The decoder architecture is defined in VHDL and the circuit is simulated and synthesized on Xilinx 14.7

A Form of List Viterbi Algorithm for Decoding Convolutional Codes

Viterbi algorithm is a maximum likelihood decoding algorithm. It is used to decode convolutional code in several wireless communication systems, including Wi-Fi. The standard Viterbi algorithm gives just one decoded output, which may be correct or incorrect. Incorrect packets are normally discarded thereby necessitating retransmission and hence resulting in considerable energy loss and delay. Some real-time applications such as Voice over Internet Protocol (VoIP) telephony do not tolerate excessive delay. This makes the conventional Viterbi decoding strategy sub-optimal. In this regard, a modified approach, which involves a form of List Viterbi for decoding the convolutional code is investigated. The technique employed combines the bit-error correction capabilities of both the Viterbi algorithm and the Cyclic Redundancy Check (CRC) procedures. It first uses a form of ‘List Viterbi Algorithm’ (LVA), which generates a list of possible decoded output candidates after the trellis search. The CRC check is then used to determine the presence of correct outcome. Results of experiments conducted using simulation shows considerable improvement in bit-error performance when compared to classical approach

Implementasi dan Pengujian Algoritma Viterbi pada Platform Labview

Penelitian ini bertujuan untuk melakukan implementasi dan pengujian dekoder Viterbi pada platform Labview. Algoritma Viterbi yang digunakan merupakan komponen wajib pada standar wireless LAN IEEE 802.11. Pengujian dilakukan dengan membuat convolutional encoder untuk menghasilkan deretan bit yang merupakan masukan bagi dekoder Viterbi. Sebelum dimasukkan ke dekoder viterbi, deretan bit tersebut melewati model kanal AWGN dan model kanal Rayleight flat fading. Dari hasil pengujian diperoleh unjuk kerja bit error rate (BER) 10-6 pada nilai signal to noise ratio (SNR) 8,6dB di kanal AWGN. Unjuk kerja tersebut dapat ditingkatkan dengan memperbesar nilai traceback. Sedangkan pada model kanal Rayleight flat fading untuk menghasilkan unjuk kerja BER 10-4 diperlukan SNR 7dB lebih tinggi dibandingkan SNR pada kanal AWGN. Dibandingkan dengan penelitian lainnya yang sejenis, unjuk kerja yang diperoleh dari hasil pengujian menggunakan Labview tidak terpaut jauh dengan pengujian menggunakan platform lainnya

High- speed- Low-Power Viterbi Decoder Design

High - speed, low - power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. We propose a pre - computation architecture incorporated with - algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre - computation steps is also given in the paper. Implementation result of a VD for a rate - 3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces th e power consumption

Low Power Register Exchange Viterbi Decoder for Wireless Applications

Since the invention of wireless telegraphy by Marconi in 1897, wireless technology has not only been enhanced, but also has become an integral part of our everyday lives. The first wireless mobile phone appeared around 1980. It was based on first generation analog technology that involved the use of Frequency Division Multiple Access (FDMA) techniques. Ten years later, second generation (2G) mobiles were dependent on Time Division Multiple Access (TDMA) techniques and Code Division Multiple Access (CDMA) techniques. Nowadays, third generation (3G) mobile systems depend on CDMA techniques to satisfy the need for faster, and more capacious data transmission in mobile wireless networks. Wideband CDMA (WCDMA) has become the major 3G air interface in the world. WCDMA employs convolutional encoding to encode voice and MPEG4 applications in the baseband transmitter at a maximum frequency of 2Mbps. To decode convolutional codes, Andrew Viterbi invented the Viterbi Decoder (VD) in 1967. In 2G mobile terminals, the VD consumes approximately one third of the power consumption of a baseband mobile transceiver. Thus, in 3G mobile systems, it is essential to reduce the power consumption of the VD. Conceptually, the Register Exchange (RE) method is simpler and faster than the Trace Back (TB) method for implementing the VD. However, in the RE method, each bit in the memory must be read and rewritten for each bit of information that is decoded. Therefore, the RE method is not appropriate for decoders with long constraint lengths. Although researchers have focused on implementing and optimizing the TB method, the RE method is focused on and modified in this thesis to reduce the RE method's power consumption. This thesis proposes a novel modified RE method by adopting a pointer concept for implementing the survivor memory unit (SMU) of the VD. A pointer is assigned to each register or memory location. The contents of thepointer which points to one register is altered to point to a second register, instead of copying the contents of the first register to the second. When the pointer concept is applied to the RE's SMU implementation (modified RE), there is no need to copy the contents of the SMU and rewrite them, but one row of memory is still needed for each state of the VD. Thus, the VDs in CDMA systems require 256 rows of memory. Applying the pointer concept reduces the VD's power consumption by 20 percent as estimated by the VHDL synthesis tool and by the new power reduction estimation that is introduced in this work. The coding gain for the modified RE method is 2. 6dB at an SNR of approximately 10-3. Furthermore, a novel zero-memory implementation for the modified RE method is proposed. If the initial state of the convolutional encoder is known, the entire SMU of the modified RE VD is reduced to only one row. Because the decoded data is generated in the required order, even this row of memory is dispensable. The zero-memory architecture is called the MemoryLess Viterbi Decoder (MLVD), and reduces the power consumption by approximately 50 percent. A prototype of the MLVD with a one third convolutional code rate and a constraint length of nine is mapped into a Xilinx 2V6000 chip, operating at 25 MHz with a decoding throughput of more than 3Mbps and a latency of two data bits. The other problem of the VD which is addressed in this thesis is the Add Compare Select Unit (ACSU) which is composed of 128 butterfly ACS modules. The ACSU's high parallelism has been previously solved by using a bit serial implementation. The 8-bit First Input First Output (FIFO) register, needed for the storage of each path metric (PM), is at the heart of the single bit serial ACS butterfly module. A new, simply controlled shift register is designed at the circuit level and integrated into the ACS module. A chip for the new module is also fabricated