The STAR MAPS-based PiXeL detector

The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Custom built pixel sensors, their readout electronics and the detector mechanical structure are described in detail. Selected detector design aspects and production steps are presented. The detector operations during the three years of data taking (2014-2016) and the overall performance exceeding the design specifications are discussed in the conclusive sections of this paper

Construction and commissioning of a technological prototype of a high-granularity semi-digital hadronic calorimeter

A large prototype of 1.3m3 was designed and built as a demonstrator of the semi-digital hadronic calorimeter (SDHCAL) concept proposed for the future ILC experiments. The prototype is a sampling hadronic calorimeter of 48 units. Each unit is built of an active layer made of 1m2 Glass Resistive Plate Chamber(GRPC) detector placed inside a cassette whose walls are made of stainless steel. The cassette contains also the electronics used to read out the GRPC detector. The lateral granularity of the active layer is provided by the electronics pick-up pads of 1cm2 each. The cassettes are inserted into a self-supporting mechanical structure built also of stainless steel plates which, with the cassettes walls, play the role of the absorber. The prototype was designed to be very compact and important efforts were made to minimize the number of services cables to optimize the efficiency of the Particle Flow Algorithm techniques to be used in the future ILC experiments. The different components of the SDHCAL prototype were studied individually and strict criteria were applied for the final selection of these components. Basic calibration procedures were performed after the prototype assembling. The prototype is the first of a series of new-generation detectors equipped with a power-pulsing mode intended to reduce the power consumption of this highly granular detector. A dedicated acquisition system was developed to deal with the output of more than 440000 electronics channels in both trigger and triggerless modes. After its completion in 2011, the prototype was commissioned using cosmic rays and particles beams at CERN.Comment: 49 pages, 41 figure

Real-Time Digital Simulators: A Comprehensive Study on System Overview, Application, and Importance

The multifarious improvements in computational and simulation tools have brought tremendous progress in the field of designing, testing and analyzing technologies. In this paper, the technological aspects and the concept of modern real-time digital simulators are presented. The real-time simulator functions in real time, thus it produces continuous output that realistically represents the conditions of a real system. Also, in a real-time simulator the user can test physical devices. Therefore, it is of great importance to understand the features and roles of the advanced simulator technologies. Also, User-friendly system interface, easy application in system design and testing, and most importantly cost effectiveness are the most desire features for implying these simulator into a research. Therefore, this paper summarizes all significant features by considering the above-mentioned facts of some most popular, globally, and commercially available simulator technologies. Real Time Digital Simulators (RTDS), OPAL-RT, Network Torsion Machine Control (NETOMAC), dSPACE, Real-Time solution by MathWorks (xPC target, Real-Time Windows target), Power_system Online_simulation Unveil Your Analysis (POUYA) Simulator and Typhoon HIL Simulator are discussed in this review paper based on the accessibility of information. A summarization of these simulators’ background, hardware, software and communication protocols are presented. Applications of these above-mentioned simulators are also added to understand the potentials of these simulators

Characterization of Hardening by Design Techniques on Commercial, Small Feature Sized Field-Programmable Gate Arrays

In this thesis, a methodology is developed to experimentally test and evaluate a programmable logic device unde r gamma irradiation. The purpose of which is to determine the radiation effects and characterize the improvements of various hardening by design techniques. The techniques analyzed in this thesis include Error Correction Coding (ECC) and Triple Modular Redundancy (TMR). The TMR circuit includes three different functional implementations of adders compared to TMR voted circuits of those same adders. The TMR is implemented with the same functional adders and as a Functional TMR (FTMR) with three different function adders that are voted on. The three functional adders are: a behavioral adder that allows the FPGA synthesis software to create the implementation, a ripple carry adder that consists of multiple single bit full adders linked together, and a carry look ahead adder that operates the fastest by using an algorithm that creates generate and propagate signals. These adders are connected to single voter TMR and FTMR circuits to evaluate the improvements that could be obtained. The ECC circuit includes Block RAM (BRAM) and Distributed RAM memory elements that are loaded both with ECC and non-error corrected data. The circuit is designed to check for errors in memory data, stuck bit values in the memory, and the performance improvements that ECC provides the system

A Touch of Evil: High-Assurance Cryptographic Hardware from Untrusted Components

The semiconductor industry is fully globalized and integrated circuits (ICs) are commonly defined, designed and fabricated in different premises across the world. This reduces production costs, but also exposes ICs to supply chain attacks, where insiders introduce malicious circuitry into the final products. Additionally, despite extensive post-fabrication testing, it is not uncommon for ICs with subtle fabrication errors to make it into production systems. While many systems may be able to tolerate a few byzantine components, this is not the case for cryptographic hardware, storing and computing on confidential data. For this reason, many error and backdoor detection techniques have been proposed over the years. So far all attempts have been either quickly circumvented, or come with unrealistically high manufacturing costs and complexity. This paper proposes Myst, a practical high-assurance architecture, that uses commercial off-the-shelf (COTS) hardware, and provides strong security guarantees, even in the presence of multiple malicious or faulty components. The key idea is to combine protective-redundancy with modern threshold cryptographic techniques to build a system tolerant to hardware trojans and errors. To evaluate our design, we build a Hardware Security Module that provides the highest level of assurance possible with COTS components. Specifically, we employ more than a hundred COTS secure crypto-coprocessors, verified to FIPS140-2 Level 4 tamper-resistance standards, and use them to realize high-confidentiality random number generation, key derivation, public key decryption and signing. Our experiments show a reasonable computational overhead (less than 1% for both Decryption and Signing) and an exponential increase in backdoor-tolerance as more ICs are added

Building a photonic tensor core unit with an electronic interface for convolution processing

With huge amounts of data being generated every second, the demand for parallelized, high speed, and efficient computing power is rising rapidly, pushing the limits of existing computing paradigms. In this circumstance, photonic computing hardware is a promising alternative to conventional electronics with prospects of speed and remarkably power efficient at accelerating multiply-accumulate (MAC) operations. Moreover, optical computing enables massive parallelism over their electronic counter parts through wavelength division multiplexing. This work involves the design and fabrication of an integrated photonic tensor core (PTC) capable of performing 60 millon MAC operations per second. Optical computing hardware makes use of multiple electro-optic and digital-analog converters. This work also involves the design and characterisation of a dedicated electronic interface to feed data to the PTC. In order to demonstrate the application potential, we perform convolution processing on 2D images in the optical domain with the newly developed hardware

Real-Time RF-DNA Fingerprinting of ZigBee Devices Using a Software-Defined Radio with FPGA Processing

ZigBee networks are increasingly popular for use in medical, industrial, and other applications. Traditional security techniques for ZigBee networks are based on presenting and verifying device bit-level credentials (e.g. keys). While historically effective, ZigBee networks remain vulnerable to attack by any unauthorized rogue device that can obtain and present bit-level credentials for an authorized device. This research focused on utilizing a National Instruments (NI) X310 Software-Defined Radio (SDR) hosting an on-board Field Programmable Gate Array (FPGA). The demonstrations included device discrimination assessments using like-model ZigBee AVR RZUSBstick devices and included generating RF fingerprints in real-time, as an extension to AFIT\u27s RF-DNA fingerprinting work. The goal was to develop a fingerprinting process that was both 1) effective at discriminating between like-model ZigBee devices and 2) efficient for implementation in FPGA hardware. As designed and implemented, the full-dimensional FPGA fingerprint generator only utilized approximately 7% of the X310 Kintex-7 FPGA resources. The full-dimensional fingerprinting performance of using only 7% of FPGA resources demonstrates the feasibility for real-time RF-DNA fingerprint generation and like-model ZigBee device discrimination using an SDR platform

Design of the user-friendly touch screen GUI and a physical connection to an existing simulation hardware device

Práce uvádí základní informace o průmyslové sběrnici AS-Interface a popisuje její funkce. Dále se zabývá rozšířením stávajícího FTZ AS-Interface Slave Simulátoru o dotykový display, který značně usnadní ovládání tohoto simulačního nástroje. Je zde nastíněn návrh a řešení uživatelského dotykového rozhraní k tomuto simulátoru s použitím Amulet LCD modulu STK 480272C. Vývoj tohoto rozhraní je proveden pomocí GEMstudia, softwaru firmy Amulet Technologies a grafických programů. Dále tato studie pojednává o softwarové úpravě FTZ AS-i Slave Smilulátoru. Jedná se o úpravu řídícího FPGA v jazyce VHDL zajišťující komunikaci s dotykovým displejem. Poslední kapitola se týká problematiky spojené s návrhem uživatelsky přívětivé aplikace.This master’s thesis deals with fundamental principles of the industrial bus AS- Interface as well as with an extension of the FTZ AS-Interface Slave Simulator by touch panel which makes it incomparably easy to control this device. Progress and solution of the touch communication interface for this Slave Simulator have been sketched out by using Amulet LCD module STK-480272C. The design of this communication interface has been created by GEMstudio, software of Amulet Technologies and graphics programs. Further this study deals with software adjustment of FTZ AS-i Slave Simulator. The modification of controlling FPGA in VHDL programming language has been described which ensures the communication with the touch screen. Last chapter deals with questions concerning a user-friendly design of the application.

Exploring formal verification methodology for FPGA-based digital systems.

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