量子化誤差削減のためのΔΣ変調器のノイズ整形フィルタの設計

広島大学(Hiroshima University)博士(工学)Doctor of Engineeringdoctora

Performance Analysis of IIR and FIR Filters for 5G Wireless Networks

This paper analyses the performances of the Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filters. By studying the relationship between filter responses with filter orders and delay, the goal is to choose feasible filters that can accommodate more carriers in a bandwidth thus, the spectral efficiency can be increased. For IIR filtering, we employ filters namely Butterworth, Chebyshev, and Elliptic, while the Equiripple, Bohman, and Hamming are studied for FIR filtering. We evaluate these filters in terms of magnitude response, phase response and group delay, and identify the minimum filter order that characterized nearly to an ideal filter response. The results show that the IIR filter has a steep transition region when compared to the FIR filters under the similar order.  Our performance analysis showed that the IIR filters, with similar filter order of FIR filters, have also the fastest roll-off, small transition region, and low implementation cost. On the other hand, the FIR filters have linear phase response that related to group delay.  Finally, our analysis concluded that Elliptic able to suppress the sidelobes with a minimum order of 10th   and Equiripple have the fastest roll-off and narrowest transition region compare to other tested FIR filter. Thus, make these two types of filter feasible candidates to be implemented in 5G wireless networks

Noise Weighting in the Design of {\Delta}{\Sigma} Modulators (with a Psychoacoustic Coder as an Example)

A design flow for {\Delta}{\Sigma} modulators is illustrated, allowing quantization noise to be shaped according to an arbitrary weighting profile. Being based on FIR NTFs, possibly with high order, the flow is best suited for digital architectures. The work builds on a recent proposal where the modulator is matched to the reconstruction filter, showing that this type of optimization can benefit a wide range of applications where noise (including in-band noise) is known to have a different impact at different frequencies. The design of a multiband modulator, a modulator avoiding DC noise, and an audio modulator capable of distributing quantization artifacts according to a psychoacoustic model are discussed as examples. A software toolbox is provided as a general design aid and to replicate the proposed results.Comment: 5 pages, 18 figures, journal. Code accompanying the paper is available at http://pydsm.googlecode.co

Digital Signal Processing with Signal-Derived Timing: Analysis and Implementation

This work investigates two different digital signal processing (DSP) approaches that rely on signal-derived timing: continuous-time (CT) DSP and variable-rate DSP. Both approaches enable designs of energy-efficient signal processing systems by relating their operation rates to the input activity. The majority of this thesis focuses on CT-DSP, whose operations are completely digital in CT, without the use of a clock. The spectral features of CT digital signals are analyzed first, demonstrating a general pattern of the quantization noise spectrum added in CT amplitude quantization. Then the focus is narrowed to the investigations of the system characteristics and architecture of CT digital infinite-impulse-response (IIR) filters, which are barely studied in the previous work on this topic. This thesis discusses and addresses previously unreported stability issue in CT digital IIR filters with the presence of delay-line mismatches and proposes an innovative method to design high-order CT digital IIR filters with only two tap delays. Introducing an event detector allows the operation rate of a CT digital IIR filter to closely track the input activity even though it is a feedback system. For the first time, the filtered CT digital signal is converted to a synchronous digital signal. This facilitates integrating the CT digital filter and conventional discrete-time systems and expands the applications of the former. This discussion uses a computationally efficient interpolation filter to improve the signal accuracy of the synchronous digital output. On the circuit level, a new delay-cell design is introduced. It ensures low jitter, good matching, robust communication with adjacent circuits and event-independent delay. An integrated circuit (IC) with all these ideas adopted was fabricated in a TSMC 65 nm LP CMOS process. It is the first IC implementation of a CT digital IIR filter. It can process signals with a data rate up to 20 MHz. Thanks to the IIR response and the 16-bit resolution used in the system, the implemented filter can achieve a frequency response much more versatile and accurate than the CT digital filters in prior art. The implemented system features an agile power adaptive to input activity, varying from 2.32mW (full activity) to 40μW (idle) with no power-management circuitry. The second part of the thesis discusses a variable-rate DSP capable of processing samples with a variable sampling rate. The clock rate in the variable-rate DSP tracks the input sampling rate. Compared to a fixed-rate DSP, the proposed system has a lower output data rate and hence is more computationally efficient. A reconstruction filter with a variable cutoff frequency is used to reconstruct the output. The signal-to-noise ratio remains fixed when the sampling rate changes

Finite-rate control : stability and performance

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (leaves 88-91).The classical control paradigm addressed problems where communication between one plant and one controller is essentially perfect, and both have either discrete or continuous dynamics. Today, new problems in control over networks are emerging. A complex network involves an interconnection of numerous computational components where the controllers may be decentralized, and the components can have discrete or continuous dynamics. Communication links can be very noisy, induce delays, and have finite-rate constraints. Applications include remote navigation systems over the internet (eg. telesurgery) or in constrained environments (eg. deep sea/Mars exploration). These complexities demand that control be integrated with the protocols of communication to ensure stability and performance. Control over networks is recent and continues to receive growing interest. Initial work has focused on asymptotic stability under finite-rate feedback control, where the only excitation to the system is an unknown (but bounded) finite-dimensional initial condition vector. Such problems reduce to state-estimation under finite-rate constraints.(cont.) More recently, disturbance rejection limitations were derived for the same setting, assuming stochastic exogenous signals entering the system. Although these studies have contributed greatly to our understanding of such systems, input-output stability, performance analysis, and synthesis of coding schemes and controllers under finite-rate constraints remains largely untapped. In this thesis we address how finiterate control impacts input-output stability and performance, and we also construct computable methods for synthesizing controllers and coding schemes to meet control objectives. We first investigate how finite-rate feedback limits input-output stability and closed-loop performance. We assume that exogenous inputs belong to rich deterministic classes of signals, and perform analyses in a worst case setting. Since our results are derived using a robust control perspective, we are able to translate performance demands into optimization problems that can be solved to obtain quantization strategies and controllers in a streamlined manner. We then study how finite-rate feedforward control impacts finite-horizon tracking and navigation.(cont.) We derive performance limitations for each case, and illustrate time and performance tradeoffs. Finally, we investigate feedforward control over noisy discrete channels, and solve a decentralized distributed design problem involving the simultaneous synthesis of a block coding strategy and a single-input single-output linear time-invariant controller. We also illustrate delay versus accuracy tradeoffs.by Sridevi Vedula Sarma.Ph.D

Applied high resolution digital control for universal precision systems

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2008.Includes bibliographical references (p. 223-225).This thesis describes the design and characterization of a high-resolution analog interface for dSPACE digital control systems and a high-resolution, high-speed data acquisition and control system. These designs are intended to enable higher precision digital control than currently available. The dSPACE system was previously designed within the PMC Lab and includes higher resolution A/D and D/A interfaces than natively available. Characterization on the custom A/D channel demonstrates 20.1 effective bits, or a 121 dB dynamic range, and the custom D/A channel demonstrates 15.1 effective bits, or a 91 dB dynamic range. This compares to a 15.7 effective bits on the A/D dSPACE channel and 12.3 effective bits on the D/A dSPACE channel. The increased resolution is attained by higher performance hardware and oversampling and averaging the A/D channel. The sampling rate is limited to 8 kHz. The high-resolution, high-speed data acquisition and control system can sample two A/D channels at 2.5 MHz and display/save an acquired one second burst. The A/D channel is characterized at 109 dB dynamic range with a grounded input and 96 dB dynamic range, or 0.74 nm RMS over a 50 [mu]m range, with a fixtured capacitive probe. Acquisition at 2.5 MHz and closed-loop control at 625 kHz sampling rate is implemented on a National Instruments FPGA. The A/D circuit was designed and built on a custom printed circuit board around the commercially available AD7760 sigma-delta converter from Analog Devices and includes fully differential ±10 V inputs, a dedicated microcontroller to provide an initialization sequence, and digital galvanic isolation. LabVIEW FPGA code demonstrates arbitrary transfer function control implementation.(cont.) The digital platform is applied to a 1-DOF positioner to demonstrate 0.10 nm RMS control over a 10 [mu]m mechanical range when filtered to the 1.5 kHz closed-loop bandwidth, which is limited by the A/D converter architecture propagation delay.by Aaron John Gawlik.S.M

Signal processing using short word-length

Recently short word-length (normally 1 bit or bits) processing has become a promising technique. However, there are unresolved issues in sigma-delta modulation, which is the basis for 1b/2b systems. These issues hindered the full adoption of single-bit techniues in industry. Among these problems is the stability of high-order modulators and the limit cycle behaviour. More importantly, there is no adaptive LMS structure of any kind in 1b/2b domain. The challenge in this problem is the harsh quantization that prevents straightforward LMS application. In this thesis, the focus has been made on three axes: designing new single-bit DSP applications, proposing novel approaches for stability analysis, and tacking the unresolved problems of 1b/2b adaptive filtering. Two structures for 1b digital comb filtering are proposed. A ternary DC blocker structure is also presented and performanc e is tested. We also proposed a single-bit multiplierless DC-blocking structure. The stability of a single-bit high-order signma-delta modulator is studied under dc inputs. A new approach for stability analysis is proposed based on analogy with PLL analysis. Finally we succeeded in designing 1b/2b Wiener-like filtering and introduced (for the first time) three 1b/2b adaptive schemes

Digital and Mixed Domain Hardware Reduction Algorithms and Implementations for Massive MIMO

Emerging 5G and 6G based wireless communications systems largely rely on multiple-input-multiple-output (MIMO) systems to reduce inherently extensive path losses, facilitate high data rates, and high spatial diversity. Massive MIMO systems used in mmWave and sub-THz applications consists of hundreds perhaps thousands of antenna elements at base stations. Digital beamforming techniques provide the highest flexibility and better degrees of freedom for phased antenna arrays as compared to its analog and hybrid alternatives but has the highest hardware complexity. Conventional digital beamformers at the receiver require a dedicated analog to digital converter (ADC) for every antenna element, leading to ADCs for elements. The number of ADCs is the key deterministic factor for the power consumption of an antenna array system. The digital hardware consists of fast Fourier transform (FFT) cores with a multiplier complexity of (N log2N) for an element system to generate multiple beams. It is required to reduce the mixed and digital hardware complexities in MIMO systems to reduce the cost and the power consumption, while maintaining high performance. The well-known concept has been in use for ADCs to achieve reduced complexities. An extension of the architecture to multi-dimensional domain is explored in this dissertation to implement a single port ADC to replace ADCs in an element system, using the correlation of received signals in the spatial domain. This concept has applications in conventional uniform linear arrays (ULAs) as well as in focal plane array (FPA) receivers. Our analysis has shown that sparsity in the spatio-temporal frequency domain can be exploited to reduce the number of ADCs from N to where . By using the limited field of view of practical antennas, multiple sub-arrays are combined without interferences to achieve a factor of K increment in the information carrying capacity of the ADC systems. Applications of this concept include ULAs and rectangular array systems. Experimental verifications were done for a element, 1.8 - 2.1 GHz wideband array system to sample using ADCs. This dissertation proposes that frequency division multiplexing (FDM) receiver outputs at an intermediate frequency (IF) can pack multiple (M) narrowband channels with a guard band to avoid interferences. The combined output is then sampled using a single wideband ADC and baseband channels are retrieved in the digital domain. Measurement results were obtained by employing a element, 28 GHz antenna array system to combine channels together to achieve a 75% reduction of ADC requirement. Implementation of FFT cores in the digital domain is not always exact because of the finite precision. Therefore, this dissertation explores the possibility of approximating the discrete Fourier transform (DFT) matrix to achieve reduced hardware complexities at an allowable cost of accuracy. A point approximate DFT (ADFT) core was implemented on digital hardware using radix-32 to achieve savings in cost, size, weight and power (C-SWaP) and synthesized for ASIC at 45-nm technology

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient