Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2008.Includes bibliographical references (p. 223-225).This thesis describes the design and characterization of a high-resolution analog interface for dSPACE digital control systems and a high-resolution, high-speed data acquisition and control system. These designs are intended to enable higher precision digital control than currently available. The dSPACE system was previously designed within the PMC Lab and includes higher resolution A/D and D/A interfaces than natively available. Characterization on the custom A/D channel demonstrates 20.1 effective bits, or a 121 dB dynamic range, and the custom D/A channel demonstrates 15.1 effective bits, or a 91 dB dynamic range. This compares to a 15.7 effective bits on the A/D dSPACE channel and 12.3 effective bits on the D/A dSPACE channel. The increased resolution is attained by higher performance hardware and oversampling and averaging the A/D channel. The sampling rate is limited to 8 kHz. The high-resolution, high-speed data acquisition and control system can sample two A/D channels at 2.5 MHz and display/save an acquired one second burst. The A/D channel is characterized at 109 dB dynamic range with a grounded input and 96 dB dynamic range, or 0.74 nm RMS over a 50 [mu]m range, with a fixtured capacitive probe. Acquisition at 2.5 MHz and closed-loop control at 625 kHz sampling rate is implemented on a National Instruments FPGA. The A/D circuit was designed and built on a custom printed circuit board around the commercially available AD7760 sigma-delta converter from Analog Devices and includes fully differential ±10 V inputs, a dedicated microcontroller to provide an initialization sequence, and digital galvanic isolation. LabVIEW FPGA code demonstrates arbitrary transfer function control implementation.(cont.) The digital platform is applied to a 1-DOF positioner to demonstrate 0.10 nm RMS control over a 10 [mu]m mechanical range when filtered to the 1.5 kHz closed-loop bandwidth, which is limited by the A/D converter architecture propagation delay.by Aaron John Gawlik.S.M
