Evaluation of SiC Schottky diodes using pressure contacts

The thermomechanical reliability of SiC power devices and modules is increasingly becoming of interest especially for high power applications where power cycling performance is critical. Press-pack assemblies are a trusted and reliable packaging solution that has traditionally been used for high power thyristor- based applications in FACTS/HVDC, although press-pack IGBTs have become commercially available more recently. These press-pack IGBTs require anti-parallel PiN diodes for enabling reverse conduction capability. In these high power applications, paralleling chips for high current conduction capability is a requirement, hence, electrothermal stability during current sharing is critical. SiC Schottky diodes not only exhibit the advantages of wide bandgap technology compared to silicon PiN diodes, but they have significantly lower zero temperature coefficient (ZTC) meaning they are more electrothermally stable. The lower ZTC is due to the unipolar nature of SiC Schottky diodes as opposed to the bipolar nature of PiN diodes. This paper investigates the implementation and reliability of SiC Schottky diodes in press-pack assemblies. The impact of pressure loss on the electrothermal stability of parallel devices is investigated

SiC power MOSFETs performance, robustness and technology maturity

Relatively recently, SiC power MOSFETs have transitioned from being a research exercise to becoming an industrial reality. The potential benefits that can be drawn from this technology in the electrical energy conversion domain have been amply discussed and partly demonstrated. Before their widespread use in the field, the transistors need to be thoroughly investigated and later validated for robustness and longer term stability and reliability. This paper proposes a review of commercial SiC power MOSFETs state-of-the-art characteristics and discusses trends and needs for further technology improvements, as well as device design and engineering advancements to meet the increasing demands of power electronics

Real Time Failure Imaging System under Power Stress for Power Semiconductors using Scanning Acoustic Tomography (SAT)

Failure mechanism of power semiconductors is captured as a movie image under power stress to the device in non-destructive way. The new technique is realized by combining a high speed Scanning Acoustic Tomography (SAT/SAM) and electrical power supply circuit for applying the power stress to the device. Water as acoustic wave couplant in SAT system, which has been a major disadvantage of the system, is utilized as coolant for stressed power to the device. Major barriers to accomplish this system are a severe noise due to a local convection with the heat and a formation of tiny bubbles on the observation surface. These problems are solved by introducing water jet along the scanning interface. This technique enables “real-time” failure analysis.23rd European Symposium on Reliability of Electron Devices,. Failure Physics and Analysis, October 1-5, 2012, Cagliari, Ital

Reliabiltiy of devices and technologies for solid-state lighting

The role of high-power white LEDs in general lighting applications is becoming, day-by-day, increasingly important. The reliability of these devices, compared to that of conventional light sources, represents one of the keys for their development and their market penetration. It is then of fundamental importance to deeply understand the various degradation mechanisms that affect the operation of LEDs, in terms of lifetime, chromaticity characteristics and efficiency. This thesis reports the results of a research activity focused on several issues related to the reliability of LED-based lighting systems. After an initial overview on the most important theoretical concepts necessary for the understanding of the physical results, three main sections can be identified in this thesis, concerning the presentation of research activity: • The first section reports an extensive study on one of the most critical Electrical Over Stress (EOS) phenomena, called “Hot-plugging”, which occurs when an LED module is directly connected to an energized power supply and can generate current spikes up to several tens of amperes that can potentially destroy or damage the LEDs. The aim of this section is to analyze, for the first time, the nature of the current spikes generated during hot-plugging and to present a simplified model to explain the hot plugging phenomenon. The study is based on transient electrical measurements, carried out on several LED modules (fabricated by different manufacturers), connected to three different power supplies. Results reveal that the amplitude and the time constants of the current spikes are directly determined by the number of LEDs connected in series and by the output capacitance of the current driver. • Afterwards, the second section presents an extensive study on the effects of Electrostatic Discharges (ESD) on state-of-the-art GaN based LEDs, based on optical and electrical measurements carried out during the ESD events. ESD events were simulated through a Transmission Line Pulser (TLP), which generates voltage pulses with a duration of 100ns and increasing amplitude: during each pulse, spatially resolved electroluminescence measurements were carried out through a high speed EMCCD camera. These measurements allowed to identify the chip region where the discharge is localized and the change in the damaged area induced by consecutive ESD events. In addition, the current and voltage waveforms at the LED terminal were monitored during the tests; this analysis provided important information about modifications the impedance of the devices. The analysis was carried out on different types of commercially available low-power GaN-based LEDs with several differences in the manufacturing technology. Thanks to these tests, we have identified two different failure behaviors during a destructive ESD event, clearly related to the different defects in the semiconductor lattice and to structure of the chip. • The last section investigates the thermal stability of remote phosphor plates to be used in solid-state lighting systems, for the conversion of the blue light emitted by GaN-based LEDs into white light. A preliminary thermal characterization revealed that in normal conditions of blue light irradiance the phosphor plates could reach temperature levels higher than 60°C, which can affect both performance and reliability. The results of accelerated thermal stress tests indicate that high temperature levels can trigger a relevant degradation mechanism (estimated activation energy is 1.2 eV), that drastically reduces the phosphor conversion efficiency and modifies the photometric and colorimetric characteristics of the emitted white light

Etude de la fiabilité de modules à base de LEDs blanches pour applications automobile

With rapid development of Lighting Emitting Diode (LED) market, LED performancesare now suitable for automotive high beam / low beam lighting applications. Due to the need of UltraHigh Brightness (UHB-LEDs), LEDs are packaged on high thermal conductivity materials to obtainmultichip module (4 chips in series), which deliver up to 1000 lumens at 1A. Currently, several LEDtechnologies are commercially offered for the same performances, and different packaging strategieshave been implemented in terms of chip configuration, bonding, down conversion phosphor layerand mechanical protection to optimize performances. This study addresses a dedicated methodologyfor reliability analysis, applied on two LED chip packaging technologies: On the one hand, a VerticalThin Film (VTF) technology; on the other hand a Thin Film Flip Chip (TFFC). Our methodology is basedon 3 main items: Packaging technology structure, materials analysis and electro-optical and thermal multichipmodels for both technologies to understand and extract the key parameters to monitor duringageing tests. Robustness assessment tests to define operating margins, adjust accelerated life-testingconditions, and identify failures signatures. Reliability study through a 6 000 hours High Temperature Operating Life (HTOL) acceleratedtests, to predict the Mean Time To Failure (MTTF) of these new light source technologiesregarding the automotive mission profile. Linked to failure analysis, convincing failuremechanisms are proposed.Based on these results, parametric variations are compared to failure analysis results topropose failure mechanisms. The HTOL tests reveal that both LED technologies have their specificreliability behavior and failure modes: catastrophic failure and gradual failure. Predictive lifetimeestimations (L70B50) of these multichip modules give a factor 6 between both technologies.Beyond these reliability results, the multichip architecture brings new issues for Solid StateLighting (SSL) sources in automotive, as well as partial failure or unbalanced behavior after stress.These new issues are discussed through the behavior modeling of a 10 LED modules batch for bothfailure modes. Modeling results demonstrate that the predictive lifetime of a LED multichiparchitecture is directly related with the LED technology failure mode.Les composants dédiés et actuellement disponibles pour le marché automobileprésentent une grande diversité technologique tant au niveau puce que stratégie de packaging ouencore architecture module (mono-puce ou multi-puce) pour des performances équivalentes. Cetteétude s’est attachée à développer une méthodologie d’évaluation de la fiabilité de deux filièrestechnologiques particulières de modules de LEDs multi-puce : l’une intègre une technologie verticale(VTF pour Vertical Thin Film) tandis que la seconde est focalisée sur une structure par puce montéeretournée(TFFC pour Thin Film Flip Chip). La méthodologie s’articule autour de trois principaux axes:· La connaissance des structures et le développement de modèles électro-optiques et thermiquesmulti-puce permettant d’extraire les paramètres clés à suivre au travers d’un panel varié detechniques d’analyse physique et non-destructives incluant les aspects électriques, optiques,thermiques….· Une analyse comportementale de robustesse par paliers afin de dégager les margesopérationnelles de fonctionnement ainsi que les modes et les signatures caractéristiques dedéfaillance.· Une étude de fiabilité conduite à partir de différents régimes de contraintes accélérées pourestimer les durées de vie moyennes de ces nouveaux composants en environnement automobileet l’impact au niveau système.Les résultats mettent en évidence une durée de vie très dépendante de la filière technologique(facteur 6 entre les deux filières étudiées). Les analyses de défaillance ont permis d’identifierprécisément les comportements de ces nouvelles sources d’éclairage pour dégager des indicateursprécoces de défaillance. Enfin, des préconisations ont été extraites afin de fiabiliser les futursprojecteurs à sources LEDs de puissance pour les applications en automobile

Graphics Processing Unit-Based Computer-Aided Design Algorithms for Electronic Design Automation

The electronic design automation (EDA) tools are a specific set of software that play important roles in modern integrated circuit (IC) design. These software automate the design processes of IC with various stages. Among these stages, two important EDA design tools are the focus of this research: floorplanning and global routing. Specifically, the goal of this study is to parallelize these two tools such that their execution time can be significantly shortened on modern multi-core and graphics processing unit (GPU) architectures. The GPU hardware is a massively parallel architecture, enabling thousands of independent threads to execute concurrently. Although a small set of EDA tools can benefit from using GPU to accelerate their speed, most algorithms in this field are designed with the single-core paradigm in mind. The floorplanning and global routing algorithms are among the latter, and difficult to render any speedup on the GPU due to their inherent sequential nature. This work parallelizes the floorplanning and global routing algorithm through a novel approach and results in significant speedups for both tools implemented on the GPU hardware. Specifically, with a complete overhaul of solution space and design space exploration, a GPU-based floorplanning algorithm is able to render 4-166X speedup, while achieving similar or improved solutions compared with the sequential algorithm. The GPU-based global routing algorithm is shown to achieve significant speedup against existing state-of-the-art routers, while delivering competitive solution quality. Importantly, this parallel model for global routing renders a stable solution that is independent from the level of parallelism. In summary, this research has shown that through a design paradigm overhaul, sequential algorithms can also benefit from the massively parallel architecture. The findings of this study have a positive impact on the efficiency and design quality of modern EDA design flow

Estudio de la fiabilidad mediante ensayos acelerados de diodos ultravioletas de alta potencia

Durante los últimos años la utilización de los LEDs (Light Emitting Diodes) ha aumentado de forma muy importante siendo hoy en día una alternativa real a los sistemas de iluminación tradicionales. La iluminación basada en LEDs se está utilizando ampliamente en automoción, arquitectura, aplicaciones domésticas y señalización debido a su alta fiabilidad, pequeño tamaño y bajo consumo. La evaluación de la fiabilidad de los LEDs es un tema clave previo a la comercialización o a la puesta en marcha del LED en una nueva aplicación. La evaluación de la fiabilidad de dispositivos requiere ensayos acelerados para obtener resultados de fiabilidad en un periodo de tiempo aceptable, del orden de pocas semanas. En éste proyecto se estudia la fiabilidad de dos tipos diferentes de LEDs ultravioleta, que pueden sustituir a las lámparas UV convencionales, para diferentes condiciones de trabajo y diferentes condiciones ambientales. Se hace un seguimiento de la evolución de los LEDs UV durante cientos horas de ensayo acelerado para obtener resultados y conclusiones acerca de la degradación que sufren. La memoria del proyecto fin de carrera se ha estructurado en siete capítulos. Tres de ellos son teóricos, otros tres prácticos y finalmente uno sobre el presupuesto. El primero explica la introducción y la evolución del diodo LED, el segundo introduce la fiabilidad explicando los modelos más utilizados para analizar los ensayos y el tercero es un breve tema acerca de los ensayos acelerados. Los otros tres capítulos son orientados a los experimentos realizados en este Proyecto Fin de Carrera. Uno trata sobre la descripción del ensayo acelerado realizado, otro analiza los resultados obtenidos, el siguiente analiza las conclusiones y el último el presupuesto. ABSTRACT. For the last years, the use of LEDs (Light Emitting Diodes) has increased significantly, being nowadays a real alternative to traditional lighting systems. Lighting based on LEDs is being extensively used in automotive, domestic applications and signaling due to its high reliability small size and low power consumption. The evaluation of LEDs reliability is a key issue before marketing or launching a new application. The reliability evaluation of devices requires accelerated tests to obtain reliability results in an acceptable period of time, for the order of few weeks. In this project the reliability of two different types of UV LEDs, which can replace conventional UV lamps for different conditions and different environmental conditions is studied. The evolution of LEDs UV is tracked during hundred hours of accelerated test to obtain the results and conclusions about the degradation suffered. The memory of the final project has been structured into seven chapters. Three of them are theorical another three are experimental and the last one about estimates. The first explains the introduction and development of LED, the second introduces the reliability explaining the most used models to analyze the tests and the third is a brief topic about the accelerated tests. The other three chapters are oriented to the experiments done in this PFC. One explains the description of the accelerated test we have done, another analyzes the results obtained, the following one exposes the conclusions and the last one the estimates

Optimização dinâmica da tensão de alimentação e da frequência de operação em sistemas electrónicos digitais

À medida que a tecnologia de circuitos integrados CMOS é exposta à miniaturização, surgem diversos problemas no que diz respeito à fiabilidade e performance. Efeitos tais como o BTI (Bias Thermal Instability), TDDB (Time Dependent Dielectric Breakdown), HCI (Hot Carrier Injection), EM (Electromigration) degradam os parâmetros físicos dos transístores CMOS e por sua vez alteram as propriedades eléctricas dos mesmos ao longo do tempo. Esta deterioração é chamada de envelhecimento e estes efeitos são cumulativos e têm um grande impacto na performance do circuito, especialmente se ocorrerem outras variações paramétricas, como as variações de processo, temperatura e tensão de alimentação. Estas variações são conhecidas por variações PVTA (variações no Processo de Fabricação do circuito integrado [P], na Tensão de Alimentação [V], na Temperatura [T] e variações provocadas pelo Envelhecimento dos circuitos [A]) e podem desencadear erros de sincronismo durante a vida do produto (circuito integrado digital). O trabalho apresentado nesta dissertação tem por objectivo primordial o desenvolvimento de um sistema que optimize a operação ao longo da vida de circuitos integrados digitais síncronos de forma dinâmica. Este sistema permite que os circuitos sejam optimizados de acordo com as suas necessidades: (i) Diminuir a dissipação de potência, por reduzir a tensão de alimentação para o valor mais baixo que garante a operação sem erros; ou (ii) Aumentar o desempenho/performance, por aumentar a frequência de operação até ao limite máximo no qual não ocorrem erros. A optimização dinâmica da operação ao longo da vida de circuitos integrados digitais síncronos é alcançada através de um controlador, um bloco de sensores globais e por vários sensores locais localizados em determinados flip-flops do circuito. A nova solução tem como objectivo utilizar os dois tipos de sensores atrás mencionados, globais e locais, para possibilitar a previsão de erros de performance de uma forma mais eficaz, que possibilite a activação de mecanismos que impeçam a ocorrência de erros durante o tempo de vida útil de um circuito, e dessa forma permitindo optimizar constantemente o seu funcionamento. Assim é exequível desenvolver circuitos que operem no limite das suas capacidades temporais, sem falhas, e com a utilização de margens de erro pequenas para admitir as variações de performance provocadas por variações no processo de fabrico, na tensão de alimentação, na temperatura ou o envelhecimento. Foi também desenvolvido um sistema de controlo que permite, depois da detecção de um potencial erro, desencadear um processo para diminuir a frequência do sinal de relógio do sistema, ou aumentar a tensão de alimentação, evitando que o erro ocorra. Apesar de existirem outras técnicas de controlo dinâmico da operação de circuitos integrados tais como DVS (Dynamic Voltage Scaling), de DFS (Dynamic Frequency Scaling), ou ambas (DVFS – Dynamic Voltage and Frequency Scaling), estas técnicas ou são de muito complexa implementação, ou apresentam margens de segurança elevadas, levando a soluções em que a operação do circuito não está optimizada. A solução desenvolvida neste trabalho, em que se utilizam sensores preditivos locais e globais os quais são sensíveis ao envelhecimento a longo prazo ocorrido nos circuitos, constitui uma novidade no estado da técnica relativamente ao controlo de sistemas de DVS e/ou DFS. Outro aspecto importante é que neste trabalho desenvolveu-se um método de ajuste da tensão de alimentação ou da frequência, o qual é sensível ao envelhecimento a longo prazo dos circuitos, utilizando sensores locais e globais. O controlador permite a optimização da performance dos circuitos através do aumento da frequência de operação até ao limite máximo que ainda evita a ocorrência de erros e a optimização de consumo de energia através da redução da tensão de alimentação (VDD) para o valor mínimo que ainda previne a ocorrência de erros. Através de uma análise de previsão de envelhecimento, são identificados os caminhos críticos, bem como os caminhos que envelhecem mais rápido e que se tornarão críticos com o envelhecimento do circuito. Uma vez identificados os caminhos críticos, irão ser inserido os sensores locais através da substituição dos flip-flops que terminam os caminhos críticos identificados por novos flip-flops que incluem sensores de performance e de envelhecimento. É de referenciar que estes sensores são preditivos, ou seja, que sinalizam precocemente os erros de performance, antes de eles ocorrerem nos flip-flops que capturam os caminhos críticos. A arquitectura dos sensores propostos é tal que as variações PVTA que ocorrem sobre eles fazem aumentar a sua capacidade de prever o erro, ou seja, os sensores vão-se adaptando ao longo da sua vida útil para aumentarem a sua sensibilidade. Os sensores locais têm como função realizar a calibração dos sensores globais, bem como realizar a monitorização constante dos atrasos nos caminhos mais longos do circuito, sempre que estes são activados. A função dos sensores globais é a realização da monitorização periódica ou quando solicitado dos atrasos no circuito digital. Ambos os tipos de sensores, os sensores globais como os locais podem desencadear ajustes na frequência ou na tensão de alimentação. Os sensores globais são compostos por uma unidade de controlo do sensor global, que recebe ordens do controlador do sistema para iniciar a análise ao desempenho do circuito e gera os sinais de controlo para a operação de análise global do desempenho e por duas cadeias de portas (uma com portas NOR e outra com portas NAND), com tempos de propagação superiores aos caminhos críticos que se esperam vir a ter no circuito durante a sua vida útil. Ambos os caminhos irão, presumivelmente, envelhecer mais que os caminhos críticos do circuito quando sujeitos ao efeito BTI (que influencia fortemente a degradação do Vth dos transístores [NBTI/NORs e PBTI/NANDs]). Ao longo das duas cadeias, diversos sinais à saída de algumas portas NOR e NAND são ligados a células de sensores globais, criando diversos caminhos fictícios com diferentes tempos de propagação. As saídas dos sensores das duas cadeias formam duas saídas de dados do sensor global. A fim de se alcançar a optimização do desempenho do circuito, são realizados testes de calibração dos sensores, onde são estimulados alguns caminhos críticos no circuito (através de um teste determinístico) e, simultaneamente é realizada a análise do desempenho pela unidade de sensores globais. Este procedimento, permite definir o limite máximo (mínimo) para frequência (tensão de alimentação) sem que os sensores locais sejam sinalizados. Esta informação da frequência (tensão) é guardada num registo do controlador (registo V/F) e corresponde à frequência (tensão) normal de funcionamento. Este teste também permite determinar quais os caminhos fictícios nas duas cadeias que apresentam tempos de propagação semelhantes aos caminhos críticos do circuito. Esta informação também é guardada em dois registos no controlador do sistema (registos GSOsafe), que indicam o estado das saídas dos controladores globais para a operação optimizada do circuito. Durante a vida útil do circuito, o controlador do sistema de optimização procede ao ajuste automático da frequência (ou da tensão de alimentação) do circuito, caso o controlador dos sensores globais detecte uma alteração em relação à operação correcta em memória, alterando o conteúdo do registo que guarda a frequência (tensão) de trabalho. Se por ventura ocorrer a sinalização de um sensor local e não existir nenhuma sinalização para alteração do desempenho pelos sensores globais, quer dizer que o circuito pode ter envelhecido mais que os caminhos fictícios dos sensores globais, pelo que a frequência (tensão de alimentação) de funcionamento deve ser alterada, mas também deve existir uma actualização nos registos que guardam a saída correcta dos sensores globais. É de salientar que, se os caminhos fictícios envelhecem mais do que o circuito, as margens de segurança (time slack) existentes vão sendo aumentadas ao longo da vida do circuito, tratando-se de uma segurança positiva. Mas, se existir a possibilidade do envelhecimento ser maior nos caminhos do circuito, a existência dos sensores locais a monitorizar a todo o tempo o desempenho do circuito, garantem que o sistema pode aprender com as sinalizações e adaptar-se às novas condições de operação ao longo da vida útil do circuito. Enquanto a monitorização efectuada pelo bloco de sensores globais fornece uma avaliação grosseira do estado de funcionamento do circuito, a monitorização efectuada pelos sensores locais, quando activados, fornece uma avaliação fina sobre qual a performance do circuito para que não ocorram erros funcionais. As novidades apresentadas neste trabalho são no mecanismo de controlo que permite a optimização dinâmica da tensão ou da frequência, e na arquitectura e funcionamento do sensor global a inserir no circuito. No que diz respeito ao mecanismo de controlo do sistema de optimização dinâmica, as novidades são: (i) na utilização conjunta de sensores locais e globais para garantir níveis de optimização elevados, (ii) na utilização de sensores preditivos (globais e locais) que previnem os erros de ocorrerem e (iii) na utilização de sensores sensíveis ao envelhecimento do circuito ao longo da sua vida útil. Em relação ao sensor global para monitorização de variações PVTA a novidade consiste (iv), na apresentação de sensores para a degradação nos transístores PMOS e de sensores para a degradação nos transístores NMOS. Este método de optimização e as topologias apresentadas podem ser desenvolvidas e utilizadas com outros tipos de flip-flops, ou empregando outros tipos de sensores, ou outros caminhos fictícios nos sensores globais, sem prejuízo do método global de optimização que conjuga os dois tipos de sensores, globais e locais, para optimizar a tensão de alimentação e a frequência de operação. É proposta uma nova arquitectura para um flip-flop com correcção de erros de atraso (DFC-FF / AEPDFC-FF) com e sem previsão de erros adaptativa para realizar a correcção/monitorização e correcção on-line da perda de performance a longo prazo de sistemas digitais CMOS, independentemente da sua causa. O DFC-FF integra um FF do tipo TG-MSFF (Transmission Gate Master Slave Flip-Flop) e um sensor de correcção de erros (CES) dos quais são apresentados duas propostas. O AEPDFC-FF é composto por DFC-FF e um sensor de envelhecimento. A variabilidade tornou-se na principal causa de falha dos circuitos digitais quando a tecnologia evoluiu para as escalas nanométricas. As reduzidas dimensões físicas dos novos transístores e o aumento na complexidade dos circuitos integrados tornou os novos circuitos mais susceptíveis a variações no processo de fabrico, nas condições de operação e operacionais, tendo como consequência o fabrico de dispositivos mais frágeis, com maior probabilidade de falharem nos primeiros meses de vida, e com tempos de vida útil esperados inferiores aos das tecnologias anteriores. Face a outras propostas, uma das principais vantagens do DFC-FF é que a a perda de performance do próprio sensor melhora a sua capacidade de correcção de erros. Os efeitos do envelhecimento, do aumento de temperatura e da diminuição na tensão de alimentação (VTA), aumentam a janela de correcção, permitindo que o DFC-FF possa estar sempre ligado sem comprometer o seu funcionamento. O conceito, estudado e desenvolvido em tecnologia de 65nm, pode ser transportado posteriormente para nanotecnologias mais recentes, usando MOSFETs de menor dimensão, uma vez que a arquitectura do sensor é transversal a toda a tecnologia CMOS.Universidade do Algarve, Instituto Superior de Engenhari

Characterization, modeling and reliability of RF MEMS Switches and Photovoltaic Silicon Solar Cells

The main goal of this thesis is the failure and reliability investigation of RF-MEMS switches and photovoltaic solar cells. For technical developer people the reliability issue is often consider a secondary problem in electronic devices since it is not considered an important factor in the production chain. This concept is changing is the last years because reliability studies are considered an important technological step to improve the production process. This fact is confirmed by the investments that companies adopt to test their products. In the particular case of this thesis, we can easily mention the solar cell production line where the cells are subjected to reliability tests that extrapolate the efficiency and the fill factor in order to study the performances and to consequently improve the production process. Concerning RF MEMS Wireless communication systems for space applications require electronic components with a high level of reliability, a low power consumption and they should be as small as possible in order to be better integrated in satellites. Radio Frequency Micro Electro Mechanical System (RF-MEMS) can be considered one of the best candidates to comply with previous requirements and, under certain conditions, they can completely replace an entire solid-state circuit. RF-MEM devices in general are characterized by a good miniaturization, an easily integration in a standard solid-state circuit, an almost zero power consumption, a good RF linearity and a high quality factor Q. Concerning RF-MEMS switches RF performances, they exhibit a very low insertion loss, lower than 0.1 dBm up to 60 GHz and, at the same time, a good isolation, more than 20 dBm. From an electrical and mechanical point of view the power consumption of these switches is close to zero because of an “on-state” current around pA and they are almost unaffected by high level of acceleration or deceleration because of their mass that is extremely small. The possibility to integrate the production of these devices in the standard foundry silicon processes and their integration with mature semiconductor technology are a great advantage for their spread making possible to produce them in an easy and cheap way. Over the last 10 years important developments on MEMS switches have been done all over the world. As a matter of fact, these switches are quite attractive since they combine excellent RF performances and low power consumption of mechanical switches with the small size and low weight of semiconductor devices. However, the appearance of MEMS switches on the market has been hindered by the need for specific packaging as well as by reliability issues. Reliability is a major issue for any satellite since it is almost impossible to envisage any repair work once the spacecraft has been launched. Hence, reliability is a key driver when designing any RF equipment. If we consider a RF-MEMS switch, we have to guarantee that his electromechanical performances will be the same after an intensive usage in harsh environment, for instance after millions or billions of cycles and after the exposure to different kind of radiations. In case of their application in a redundancy scheme, they have to be completely operative even after a long period of activity or inactivity. The aim of this thesis is to perform an electrical characterization and several reliability tests on different kind of RF-MEMS switches in order to analyze which are the weaknesses and the strengths of this new technology. Electrical characterizations have been done using two different measurement systems. The first, based on a vector network analyzer and a power supply, has been used to test the RF performances of the devices and to extract the actuation and deactuation voltages. The second set up, based on the internal RF signal generator of the VNA, an 8-GHz digital signal oscilloscope and a profilometer (polytec MSA 500), has been used to characterize the electrical performances like actuation time, release delay and dynamic performances. Cycling stress, one of the most common test used to understand the robustness of this kind of devices, has been performed on different topologies of switch in order to better understand how some parameters of the RF MEMS switch, such as the shape of the beams or the actuation voltage, impact on the reliability of the device. Furthermore, the influence of continuous actuation stress on the reliability of dielectric-less switches has been investigated, comparing different designs and studying the variation of the main electrical parameters induced by the stress and the successive recovery phase. Concerning PV solar cells A solar cell, or photovoltaic cell, is an electrical device that converts the energy of light directly into electricity by the photovoltaic effect. The operation of a photovoltaic (PV) cell requires 3 basic attributes: (i) the absorption of light, generating either electron-hole pairs or excitons, (ii) the separation of charge carriers of opposite types and (iii) the extraction of those carriers to an external circuit. Over the last decades, many research groups have tried to improve the conversion processes in order to increase the efficiency of solar cells and to reduce the parasitic effects that limit the energy conversion. This has generated a real challenge to the best conversion efficiency. The average efficiency of multicrystalline silicon solar cells at the beginning of 2014 was about 16% but in research labs different solar cells have exceeded the 20% with records over 24%. The continuous growth of the solar cells efficiency has been achieved thanks to the reliability study of the single cells and to the degradation analysis of the real photovoltaic systems. These studies have revealed the critical points of PV solar cells and have led to a constant improvement of the production processes. The aim of this thesis is the study of the reliability problems related to a single solar cell and to a string of solar cells subjected to different illumination conditions. Different characterization procedures have been developed in order to study the failure mechanisms and to study the weaknesses and the strengths of the technology. Four types of measurement set-ups have been utilized: (i) the first system is able to extract the IV curves in dark and light conditions. This simple measurement procedure has to be opportunely calibrated in order to obtain right results in term of efficiency and fill factor. (ii) The second system extracts the thermographic image of a single solar cell. It can be used to analyze hot spot and other failure mechanisms in the silicon structure. (iii) The third system extracts the electroluminescence and the photoluminescence of a single solar cell. It is able to extract and analyze the defects in the crystalline structure of the materials. (iv) The fourth is the LOANA system: a commercial tool able to extract the External Quantum Efficiency and the Internal Quantum Efficiency with the measurement of the reflectance. All these characterization procedures have been utilized to study the evolution of the failure mechanisms when a single solar cell is subjected to reverse biasing stresses. The study of the catastrophic degradation of solar cells submitted to reverse current stress is of crucial importance since the failure can lead to the rapid increase of the temperature with a consequent risk of fire and to the breaking of the entire PV system. This particular situation can occur when the PV system is not uniformly illuminated and the solar cells of the system present not uniform shunt resistance. Additional studies have been performed in the modelization of a solar cell with the two-diode model. The study and modeling of solar cells allow to obtain right results in term of efficiency and fill factor extrapolation. Moreover, the modelization allows the study of string of solar cells working in particular conditions in which the illumination level is not uniform in a whole panel. The simulations allow to predict the dangerous situations and to design appropriate prevention systems