Impact of laser attacks on the switching behavior of RRAM devices

The ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative to replace current memory technologies. However, their suitability for this kind of application, where the integrity of the data is crucial, is still under study. Among the different typology of attacks to recover information of secret data, laser attack is one of the most common due to its simplicity. Some preliminary works have already addressed the influence of laser tests on RRAM devices. Nevertheless, the results are not conclusive since different responses have been reported depending on the circuit under testing and the features of the test. In this paper, we have conducted laser tests on individual RRAM devices. For the set of experiments conducted, the devices did not show faulty behaviors. These results contribute to the characterization of RRAMs and, together with the rest of related works, are expected to pave the way for the development of suitable countermeasures against external attacks.Postprint (published version

Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement

ELECTRICAL CHARACTERIZATION, PHYSICS, MODELING AND RELIABILITY OF INNOVATIVE NON-VOLATILE MEMORIES

Enclosed in this thesis work it can be found the results of a three years long research activity performed during the XXIV-th cycle of the Ph.D. school in Engineering Science of the Università degli Studi di Ferrara. The topic of this work is concerned about the electrical characterization, physics, modeling and reliability of innovative non-volatile memories, addressing most of the proposed alternative to the floating-gate based memories which currently are facing a technology dead end. Throughout the chapters of this thesis it will be provided a detailed characterization of the envisioned replacements for the common NOR and NAND Flash technologies into the near future embedded and MPSoCs (Multi Processing System on Chip) systems. In Chapter 1 it will be introduced the non-volatile memory technology with direct reference on nowadays Flash mainstream, providing indications and comments on why the system designers should be forced to change the approach to new memory concepts. In Chapter 2 it will be presented one of the most studied post-floating gate memory technology for MPSoCs: the Phase Change Memory. The results of an extensive electrical characterization performed on these devices led to important discoveries such as the kinematics of the erase operation and potential reliability threats in memory operations. A modeling framework has been developed to support the experimental results and to validate them on projected scaled technology. In Chapter 3 an embedded memory for automotive environment will be shown: the SimpleEE p-channel memory. The characterization of this memory proven the technology robustness providing at the same time new insights on the erratic bits phenomenon largely studied on NOR and NAND counterparts. Chapter 4 will show the research studies performed on a memory device based on the Nano-MEMS concept. This particular memory generation proves to be integrated in very harsh environment such as military applications, geothermal and space avionics. A detailed study on the physical principles underlying this memory will be presented. In Chapter 5 a successor of the standard NAND Flash will be analyzed: the Charge Trapping NAND. This kind of memory shares the same principles of the traditional floating gate technology except for the storage medium which now has been substituted by a discrete nature storage (i.e. silicon nitride traps). The conclusions and the results summary for each memory technology will be provided in Chapter 6. Finally, on Appendix A it will be shown the results of a recently started research activity on the high level reliability memory management exploiting the results of the studies for Phase Change Memories

Evaluation of the colossal electroresistance (CER) effect and its application in the non-volatile Resistive Random Access Memory (RRAM)

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 79-81).Flash memory, the current leading technology for non-volatile memory (NVM), is projected by many to run obsolete in the face of future miniaturization trend in the semiconductor devices due to some of its technical limitations. Several different technologies have been developed in attempt for replacing Flash memory as the most dominant NVM technology; none of which seems to indicate significant success at the moment. Among these technologies is RRAM (Resistive Random Access Memory), a novel type of memory technology which has only recently emerged to join the race. The underlying principle of an RRAM device is based on the colossal electroresistance (CER) effect, i.e. the resistance switching behavior upon application of voltage of varying polarity and/or magnitude. This thesis aims to investigate the CER effect and how it can be designed to be a non-volatile memory as well as other novel application, e.g. memristor. The various technical aspects pertaining to this phenomenon, including the materials and the physical basis, are explored and analyzed. As a complementary to that, the market potential of the RRAM technology is also assessed. This includes the market study of memory industry, the current intellectual property (IP) landscape and some of the relevant business strategies. The production strategy (i.e. the production cost, initial investment, and pricing strategy) is then derived from the technical and market analysis evaluated earlier and with using some reasonable assumptions.by Aulia Tegar Wicaksono.M.Eng

Towards integrating chalcogenide based phase change memory with silicon microelectronics

The continued dominance of floating gate technology as the premier non-volatile memory (NVM) technology is expected to hit a roadblock due to issues associated with its inability to catch up with CMOS scaling. The uncertain future of floating gate memory has led to a host of unorthodox NVM technologies to surface as potential heirs. Among the mix is phase change memory (PCM), which is a non-volatile, resistance variable, memory technology wherein the state of the memory bit is defined by the resistance of the memory material. This research study examines novel, bilayer chalcogenide based materials composed of Ge-chalcogenide (GeTe or Ge2Se3) and Sn-chalcogenide (SnTe or SnSe) for phase change memory applications and explores their integration with CMOS technology. By using a layered arrangement, it is possible to induce phase change response in materials, which normally do not exhibit such behavior, and thus form new materials which may have lower threshold voltage and programming current requirements. Also, through the incorporation of a metal containing layer, the phase transition characteristics of the memory layer can be tailored in order to obtain in-situ, a material with optimized phase change properties. Using X-ray diffraction (XRD) and time resolved XRD, it has been demonstrated that stacked phase change memory films exhibit both structural and compositional dependency with annealing temperature. The outcome of the structural transformation of the bottom layer, is an annealing temperature dependent residual stress. By the incorporation of a Sn layer, the phase transition characteristics of Ge-chalcogenide thin films can be tuned. Clear evidence of thermally induced Ge, Sn and chalcogen inter-diffusion, has been discerned via transmission electron microscopy and parallel electron energy loss spectroscopy. The presence of Al2O3 as capping layer has been found to mitigate volatilization and metallic Sn phase separation at high temperatures. Two terminal PCM cells employing these bilayers have been designed, fabricated and tested. All devices exhibit threshold switching and memory switching behavior. By the application of suitable voltage programming pulses, RESET state switching can be accomplished in these devices, thus demonstrating single bit memory functionality. A process for integrating bilayer PCM technology with 2 µm CMOS has been designed and developed. The baseline RIT CMOS process has been modified to incorporate 12 levels of photolithography, 3 levels of metal and the addition of PCM as a BEOL process. On electrical testing, NMOS connected PCM devices exhibit switching behavior. The effect of the state (SET/RESET) of the series connected PCM cell on the drain current of the NMOS has also been investigated. It is determined that threshold switching of the PCM cell is essential in order to observe any change in MOS drain current with variation in drain voltage. Thus, successful integration of bilayer PCM with CMOS has been demonstrated

Electrical conduction and resistive switching in polymer and biodegradable nanocomposites

Modern memory devices such as static random-access memory (SRAM), dynamic random-access (DRAM), and Flash memories demonstrated inevitable limitations, i.e., large cell size (50 − 120 F2) of SRAM, accompanied by current leakage; high operating voltages of 3 V and up to 6 V for DRAM and NOR Flash, respectively; DRAM capacity should sustain enough charges (there is a limit to how small the DRAM capacitor can be) and Flash need a novel array structure. Additionally, these current memory devices contribute significantly to the world’s earth pollution. These memories still use heavy metals such as Pb, which are harmful to humans. There is a demand for a next-generation random-access memory (RAMs) having fast read and write operations as the SRAM, high density and cost-benefit as the DRAM, and nonvolatility as the Flash. Furthermore, new memory device must be compatible with on-chip computing. Resistive switching memories (ReRAMs) are an emerging memory technology with prospects of combined benefit found in all current memories. Furthermore, ReRAMs can be fabricated using any material, including organic polymers and biological materials. This gives ReRAM environmentally friendly properties and compatibility with futuristic electronics, where special mechanical properties such as transparency and flexibility are important. In this study, we conducted intense research on electrical conduction and resistive switching in biodegradable polymers such as chitosan and polyvinylpyrrolidone, and in the process, we discovered, for the first time, resistive switching in raw cow milk. First resistive switching and conduction mechanisms in spin-coated devices consisting ofcadmium telluride/cadmium selenide (CdTe/CdSe) coreshell quantum dots embedded in a chitosan active layer sandwiched between (1) aluminium (Al) and silver (Ag) and (2) indium-doped tin oxide (ITO) and Ag electrodes were studied. Here, both devices exhibited bipolar memory behavior at low (+0.70 V ) voltage, enabling both devices to be operated at low powers. The devices displayed different switching mechanisms, i.e., conductive bridge mechanism in the Al-based device and space-chargelimited driven conduction filament attributed in the ITO device. Additionally, the Al-based device showed long retention (> 103 s) and a reasonable large (> 103) ON/OFF ratio. We also observed a sweeping cycle-induced reversal of the voltage polarity of the VSET and VRESET in the Al-based device, which is a new observation. Using the same composite but changing the film deposition method, i.e., now using the drop-casting method. All devices consisting of 0.96 wt%, 0.48 wt%, 0.32 wt% and 0.24 wt% CdTe/CdSe QDs to chitosan showed ‘O-type’ memory behavior with OFF-state current conduction mechanism attributed to the hopping mechanism. However, the ON-state current in each device followed a unique mechanism, such that Ohmic behavior was observed for the device with 0.96 wt%, while linear then hopping, space-charge limited, and lastly, hopping conduction mechanisms were attributed to devices with 0.48 wt%, 0.32 wt% and 0.24 wt%, respectively. Proving that memory behavior and conduction in these devices can be exploited by controlling the amount of CdTe/CdSe. Next, we investigated the effect of molybdenum(IV) sulfide (MoS2) on both conduction and memory behavior in polyvinylpyrrolidone (PVP) by fabricating various ReRAM devices using (1) plain MoS2 (device A), (2) plain PVP (device B), (3) PVP and MoS2 bilayer (device C), and (4) PVP +MoS2 nanocomposites with 10 wt% (device D), 20 wt% (device E), 30 wt% (device F) and 40 wt% (device G) MoS2 fabricated with Al and Ag as bottom and top electrodes, respectively. We did not observe switching in devices A and B. Device C showed a combination of bipolar and threshold switching at 0.40 V . Device G portrayed bipolar switching at 0.56 V . In Device C, space charge-limited conduction while Ohmic behavior followed by trapping of charge before switching was noticed in device G. Both devices C and G showed reasonably (≥ 102) ON/OFF ratio. In the nanocomposite devices, we observed that an increase in MoS2 content increased electrical conductivity in the Ohmic region, leading to threshold switching at 30 wt% (device F) and ultimately bipolar switching at 40 wt% (device G). These studies showed that both switching and conduction mechanisms are sensitive to the type and composition of the active layer in the devices studied. Next, we investigated resistive switching in chitosan/PVP composite as the active layers sandwiched between Al and Ag electrodes. ReRAMs with active layers consisting of 1 : 3, 1 : 1, and 3 : 1 chitosan to PVP ratios were studied. Asymmetric threshold switching with only the negative voltage bias was obtained for the device with a chitosan to PVP ratio of 1 : 3. The 1 : 1 chitosan to PVP ratio device showed optimal memory behavior with bipolar switching with low (0.28 V ) switching voltage in the first cycle, followed by asymmetric threshold switching during the second cycle and back to bipolar switching. We did not observe memory behavior in the 3 : 1 chitosan to PVP-based device. Electrochemical conduction metalization was attributed to the switching mechanism in the device with a 1 : 1 ratio of chitosan to PVP. Our results reveal the applicability of chitosan and PVP blend in memory device fabrication and that both the memory and switching can be exploited by varying the ratio of chitosan to PVP in the composite. Lastly, we fabricated the first resistive switching memory devices that use raw organic cow milk as active layers. Our devices comprised fat-free, medium cream, and full cream raw cow milk active layers sandwiched between ITO and Ag. All devices showed low switching voltages, with the medium fat milk-based device showing the lowest VSET = +0.45 V and VRESET = −0.25 V . Additionally, the medium fat-based device showed an ‘S-type’ memory mode attributed to the space-charge-limited conduction mechanism. Alternatively, fat-free and fill-cream-based devices both showed ‘O-type’ memory behavior attributed to hopping conduction. EDS analysis of all active layers revealed a relatively higher weight percentage of metallic ions in the medium fat milk film than in fat-free and full-cream milk films, which explains the different behaviors. These devices combine biodegradability and low power characteristics that are important for green computing.PhysicsPh.D. (Physics

Nanoparticle Engineering for Chemical-Mechanical Planarization

Increasing reliance on electronic devices demands products with high performance and efficiency. Such devices can be realized through the advent of nanoparticle technology. This book explains the physicochemical properties of nanoparticles according to each step in the chemical mechanical planarization (CMP) process, including dielectric CMP, shallow trend isolation CMP, metal CMP, poly isolation CMP, and noble metal CMP. The authors provide a detailed guide to nanoparticle engineering of novel CMP slurry for next-generation nanoscale devices below the 60nm design rule. This comprehensive text also presents design techniques using polymeric additives to improve CMP performance

Resistance switching devices based on amorphous insulator-metal thin films

Nanometallic devices based on amorphous insulator-metal thin films are developed to provide a novel non-volatile resistance-switching random-access memory (RRAM). In these devices, data recording is controlled by a bipolar voltage, which tunes electron localization length, thus resistivity, through electron trapping/detrapping. The low-resistance state is a metallic state while the high-resistance state is an insulating state, as established by conductivity studies from 2K to 300K. The material is exemplified by a Si3N4 thin film with randomly dispersed Pt or Cr. It has been extended to other materials, spanning a large library of oxide and nitride insulator films, dispersed with transition and main-group metal atoms. Nanometallic RRAMs have superior properties that set them apart from other RRAMs. The critical switching voltage is independent of the film thickness/device area/temperature/switching speed. Trapped electrons are relaxed by electron-phonon interaction, adding stability which enables long-term memory retention. As electron-phonon interaction is mechanically altered, trapped electron can be destabilized, and sub-picosecond switching has been demonstrated using an electromagnetically generated stress pulse. AC impedance spectroscopy confirms the resistance state is spatially uniform, providing a capacitance that linearly scales with area and inversely scales with thickness. The spatial uniformity is also manifested in outstanding uniformity of switching properties. Device degradation, due to moisture, electrode oxidation and dielectrophoresis, is minimal when dense thin films are used or when a hermetic seal is provided. The potential for low power operation, multi-bit storage and complementary stacking have been demonstrated in various RRAM configurations.Comment: 523 pages, 215 figures, 10 chapter