The Nyquist criterion: a useful tool for the robust design of continuous-time ΣΔ modulators

This paper introduces a figure of merit for the robustness of continuous-time sigma-delta modulators. It is based on the Nyquist criterion for the equivalent discrete-time (DT) loop filter. It is shown how continuous-time modulators can be designed by optimizing this figure of merit. This way modulators with increased robustness against variations in the noise-transfer function (NTF) parameters are obtained. This is particularly useful for constrained systems, where the system order exceeds the number of design parameters. This situation occurs for example due to the effect of excess loop delay (ELD) or finite gain bandwidth (GBW) of the opamps. Additionally, it is shown that the optimization is equivalent to the minimization of H_infinity, the maximum out-of-band gain of the NTF. This explains why conventional design strategies that are based on H_infinity, such as Schreier’s approach, provide quite robust modulator designs in the case of unconstrained architectures

Linear phase cosine modulated maximally decimated filter banks with perfect reconstruction

We propose a novel way to design maximally decimated FIR cosine modulated filter banks, in which each analysis and synthesis filter has a linear phase. The system can be designed to have either the approximate reconstruction property (pseudo-QMF system) or perfect reconstruction property (PR system). In the PR case, the system is a paraunitary filter bank. As in earlier work on cosine modulated systems, all the analysis filters come from an FIR prototype filter. However, unlike in any of the previous designs, all but two of the analysis filters have a total bandwidth of 2π/M rather than π/M (where 2M is the number of channels in our notation). A simple interpretation is possible in terms of the complex (hypothetical) analytic signal corresponding to each bandpass subband. The coding gain of the new system is comparable with that of a traditional M-channel system (rather than a 2M-channel system). This is primarily because there are typically two bandpass filters with the same passband support. Correspondingly, the cost of the system (in terms of complexity of implementation) is also comparable with that of an M-channel system. We also demonstrate that very good attenuation characteristics can be obtained with the new system

A New Approach for Designing Orthogonal Wavelets for Multicarrier Applications

yesThe Daubechies, coiflet and symlet wavelets, with properties of orthogonal wavelets are suitable for multicarrier transmission over band-limited channels. It has been shown that similar wavelets can be constructed by Lagrange approximation interpolation. In this work and using established wavelet design algorithms, it is shown that ideal filters can be approximated to construct new orthogonal wavelets. These new wavelets, in terms of BER behave slightly better than the wavelets mentioned above, and much better than biorthogonal wavelets, in multipath channels with additive white Gaussian noise (AWGN). It is shown that the construction, which uses a simple simultaneous solution to obtain the wavelet filters from the ideal filters based on established wavelet design algorithms, is simple and can easily be reproduced

Basics of RF electronics

RF electronics deals with the generation, acquisition and manipulation of high-frequency signals. In particle accelerators signals of this kind are abundant, especially in the RF and beam diagnostics systems. In modern machines the complexity of the electronics assemblies dedicated to RF manipulation, beam diagnostics, and feedbacks is continuously increasing, following the demands for improvement of accelerator performance. However, these systems, and in particular their front-ends and back-ends, still rely on well-established basic hardware components and techniques, while down-converted and acquired signals are digitally processed exploiting the rapidly growing computational capability offered by the available technology. This lecture reviews the operational principles of the basic building blocks used for the treatment of high-frequency signals. Devices such as mixers, phase and amplitude detectors, modulators, filters, switches, directional couplers, oscillators, amplifiers, attenuators, and others are described in terms of equivalent circuits, scattering matrices, transfer functions; typical performance of commercially available models is presented. Owing to the breadth of the subject, this review is necessarily synthetic and non-exhaustive. Readers interested in the architecture of complete systems making use of the described components and devoted to generation and manipulation of the signals driving RF power plants and cavities may refer to the CAS lectures on Low-Level RF.Comment: 36 pages, contribution to the CAS - CERN Accelerator School: Specialised Course on RF for Accelerators; 8 - 17 Jun 2010, Ebeltoft, Denmar

Discrete multitone modulation with principal component filter banks

Discrete multitone (DMT) modulation is an attractive method for communication over a nonflat channel with possibly colored noise. The uniform discrete Fourier transform (DFT) filter bank and cosine modulated filter bank have in the past been used in this system because of low complexity. We show in this paper that principal component filter banks (PCFB) which are known to be optimal for data compression and denoising applications, are also optimal for a number of criteria in DMT modulation communication. For example, the PCFB of the effective channel noise power spectrum (noise psd weighted by the inverse of the channel gain) is optimal for DMT modulation in the sense of maximizing bit rate for fixed power and error probabilities. We also establish an optimality property of the PCFB when scalar prefilters and postfilters are used around the channel. The difference between the PCFB and a traditional filter bank such as the brickwall filter bank or DFT filter bank is significant for effective power spectra which depart considerably from monotonicity. The twisted pair channel with its bridged taps, next and fext noises, and AM interference, therefore appears to be a good candidate for the application of a PCFB. This is demonstrated with the help of numerical results for the case of the ADSL channel

Pulse shaping methods for inter carrier interference reduction in OFDM system

The weakness of the orthogonal freuency division multiplexing (OFDM) system is susceptible to the existence of carrier frequency offset (CFO) which causes the emergence of inter carrier interference (ICI) which causes a degradation of performance OFDM systems. This study aims to apply the suggested rectangular (REC) pulse and improved sinc-power (ISP) pulse shaping methods on OFDM system and determines ICI reduction with the effects of CFO over flat fading Rayleigh channels. The performance of each pulse shaping method is evaluated and compared based on parameter ICI power vs. normalized frequency offset, signal to interference ratio (SIR) vs. normalized frequency offset and bit error rate (BER) vs. energy bit per noise (Eb/No). The simulation result in terms of BER vs. Eb/No indicated that REC and ISP pulse shaping has better performance dealing with ICI reduction compared to OFDM system no applied pulse shaping. In addition, the ISP is able to mitigate ICI better than REC

High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion

The purpose of this thesis is the proposal and implementation of data conversion open-loop architectures based on voltage-controlled oscillators (VCOs) built with ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to the newest complementary metal-oxide-semiconductor (CMOS) nodes. The scaling of the design technologies into the nanometer range imposes the reduction of the supply voltage towards small and power-efficient architectures, leading to lower voltage overhead of the transistors. Additionally, phenomena like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between devices and PVT variations) make the design of classic structures for ADCs more challenging. In recent years, time-encoded A/D conversion has gained relevant popularity due to the possibility of being implemented with mostly digital structures. Within this trend, VCOs designed with ring oscillator based topologies have emerged as promising candidates for the conception of new digitization techniques. RO-based data converters show excellent scalability and sensitivity, apart from some other desirable properties, such as inherent quantization noise shaping and implicit anti-aliasing filtering. However, their nonlinearity and the limited time delay achievable in a simple NOT gate drastically limits the resolution of the converter, especially if we focus on wide-band A/D conversion. This thesis proposes new ways to alleviate these issues. Firstly, circuit-based techniques to compensate for the nonlinearity of the ring oscillator are proposed and compared to equivalent state-of-the-art solutions. The proposals are designed and simulated in a 65-nm CMOS node for open-loop RO-based ADC architectures. One of the techniques is also validated experimentally through a prototype. Secondly, new ways to artificially increase the effective oscillation frequency are introduced and validated by simulations. Finally, new approaches to shape the quantization noise and filter the output spectrum of a RO-based ADC are proposed theoretically. In particular, a quadrature RO-based band-pass ADC and a power-efficient Nyquist A/D converter are proposed and validated by simulations. All the techniques proposed in this work are especially devoted for highbandwidth applications, such as Internet-of-Things (IoT) nodes or maximally digital radio receivers. Nevertheless, their field of application is not restricted to them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas de conversión de datos basadas en osciladores en anillos, compatibles con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación más modernos donde las estructuras digitales se ven favorecidas. La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción de la tensión de alimentación para el desarrollo de arquitecturas pequeñas y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión para saturar transistores, lo que añadido a una ganancia cada vez menor de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones de proceso, tensión y temperatura han llevado a que sea cada vez más complejo el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión A/D basada en codificación temporal ha ganado gran popularidad dado que permite la implementación de estructuras mayoritariamente digitales. Como parte de esta evolución, los osciladores controlados por tensión diseñados con topologías de oscilador en anillo han surgido como un candidato prometedor para la concepción de nuevas técnicas de digitalización. Los convertidores de datos basados en osciladores en anillo son extremadamente sensibles (variación de frecuencia con respecto a la señal de entrada) así como escalables, además de otras propiedades muy atractivas, como el conformado espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta NOT restringen la resolución del conversor, especialmente para conversión A/D en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas técnicas para aliviar este tipo de problemas. En primer lugar, se proponen técnicas basadas en circuito para compensar el efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas presentadas es también validada experimentalmente a través de un prototipo. En segundo lugar, se introducen y validan por simulación varias formas de incrementar artificialmente la frecuencia de oscilación efectiva. Para finalizar, se proponen teóricamente dos enfoques para configurar nuevas formas de conformación del ruido de cuantificación y filtrado del espectro de salida de los datos digitales. En particular, son propuestos y validados por simulación un ADC pasobanda en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente para aplicaciones de alto ancho de banda, tales como módulos para el Internet de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar de ello, son extrapolables también a otros campos como el de la instrumentación biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí

Design and FPGA implementation of digital transmission over severe ISI channels

Inter-symbol interference is one of the major factors that make the realization of high-data-rate digital communications system complex. Current designs face two main challenges: how to efficiently utilize the available bandwidth and how to reduce the hardware complexity of the transmitter and receiver. Traditional solutions use a single-band architecture. When ISI is severe, it might require an equalizer to mitigate ISI, which usually results in a high complexity and power consumption. This thesis focuses on the analysis and FPGA implementation of a multiband communication architecture. This design ensures that the channel frequency response in each sub-band is approximately flat to avoid the need of an equalizer. Specifically, a four-band architecture is presented in detail, and this design is compared with the single-band approach. First, basic theories are provided for convenience of understanding the major development in this thesis in terms of simulation and FPGA implementation. Then the channel characteristics, such as the frequency and impulse responses, are analyzed for a four-band architecture. The single- and four-band architectures are introduced separately and optimized in detail. The simulation results of both architectures are verified through FPGA implementation in the Xilinx Virtex5 development board. Finally, BERs of the two architectures are compared from both simulation and FPGA implementation results.Keywords: FPGA, DSP, ISI, MultibandKeywords: FPGA, DSP, ISI, Multiban