Finite state machine representation of digital signal processing systems

A new method for implementing digital filters is discussed. The met11od maximises the output signal to noise ratio of a filter by assigning at each of the filter variables an optimal quantization law. A filter optimised for a gaussian process is considered in detail. An error model is developed and applied to first and second order canonic form filter sections. Comparisons are drawn between the gaussian optimised filter and the equivalent fixed point arithmetic filter. The performance of gaussian optimised filters under sinusoidal input signal conditions is considered ; it is found that the gaussian optimised filter exhibits a lower approximation error than the equivalent fixed point arithmetic filter. It is shown that when high order filters are implemented as a cascade of second order sections - with if necessary one first order section - the section ordering has a very small effect on the overall signal to noise r atio performance. A similar result for the pairing of poles and zeroes is found. Bounds on the maximum limit cycle amplitude for first and second order all-pole sections are presented. It is shown that for a first order all-pole the maximum limit cycle amplitude is lower than would be expected in the equivalent fixed point arithmetic filter, whereas , for the second order all- pole the bound is twice as large. Examples of a low-pass , band-pass and wideband differentiating filter,designed using free quantization law techniques,are presented. This new design method leads to a filter whose arithmetic operations can not be performed using fixed point arithmetic hardware. Instead, the filter must be represented as a finite state machine and then implemented using sequential logic circuit synthesis techniques. The logic complexity is found to depend - amongst other considerations - on the so called state (code) assignment. Some preliminary results on this problem are presented for the case of a next state function computed using the AND/EXCLUSIVE- OR (ring-sum) logic expansion. A review of the state assignment techniques in the literature is included. A part of the state assignment problem - for the case of AND/EX'·/OR logic - requires the numerous and consequently rapid computation of the Reed-Muller Transformation. A hardware processor - designed as an add-on to a minicomputer - is described; speed comparisons are drawn with the equivalent software algorithm.Digitisation of this thesis was sponsored by Arcadia Fund, a charitable fund of Lisbet Rausing and Peter Baldwin

Investigation into digital audio equaliser systems and the effects of arithmetic and transform errors on performance

Merged with duplicate record 10026.1/2685 on 07.20.2017 by CS (TIS)Discrete-time audio equalisers introduce a variety of undesirable artefacts into audio mixing systems, namely, distortions caused by finite wordlength constraints, frequency response distortion due to coefficient calculation and signal disturbances that arise from real-time coefficient update. An understanding of these artefacts is important in the design of computationally affordable, good quality equalisers. A detailed investigation into these artefacts using various forms of arithmetic, filter frequency response, input excitation and sampling frequencies is described in this thesis. Novel coefficient calculation techniques, based on the matched z-transform (MZT) were developed to minimise filter response distortion and computation for on-line implementation. It was found that MZT-based filter responses can approximate more closely to s-plane filters, than BZTbased filters, with an affordable increase in computation load. Frequency response distortions and prewarping/correction schemes at higher sampling frequencies (96 and 192 kHz) were also assessed. An environment for emulating fractional quantisation in fixed and floating point arithmetic was developed. Various key filter topologies were emulated in fixed and floating point arithmetic using various input stimuli and frequency responses. The work provides detailed objective information and an understanding of the behaviour of key topologies in fixed and floating point arithmetic and the effects of input excitation and sampling frequency. Signal disturbance behaviour in key filter topologies during coefficient update was investigated through the implementation of various coefficient update scenarios. Input stimuli and specific frequency response changes that produce worst-case disturbances were identified, providing an analytical understanding of disturbance behaviour in various topologies. Existing parameter and coefficient interpolation algorithms were implemented and assessed under fihite wordlength arithmetic. The disturbance behaviour of various topologies at higher sampling frequencies was examined. The work contributes to the understanding of artefacts in audio equaliser implementation. The study of artefacts at the sampling frequencies of 48,96 and 192 kHz has implications in the assessment of equaliser performance at higher sampling frequencies.Allen & Heath Limite

Advanced modulation technology development for earth station demodulator applications. Coded modulation system development

A jointly optimized coded modulation system is described which was designed, built, and tested by COMSAT Laboratories for NASA LeRC which provides a bandwidth efficiency of 2 bits/s/Hz at an information rate of 160 Mbit/s. A high speed rate 8/9 encoder with a Viterbi decoder and an Octal PSK modem are used to achieve this. The BER performance is approximately 1 dB from the theoretically calculated value for this system at a BER of 5 E-7 under nominal conditions. The system operates in burst mode for downlink applications and tests have demonstrated very little degradation in performance with frequency and level offset. Unique word miss rate measurements were conducted which demonstrate reliable acquisition at low values of Eb/No. Codec self tests have verified the performance of this subsystem in a stand alone mode. The codec is capable of operation at a 200 Mbit/s information rate as demonstrated using a codec test set which introduces noise digitally. The measured performance is within 0.2 dB of the computer simulated predictions. A gate array implementation of the most time critical element of the high speed Viterbi decoder was completed. This gate array add-compare-select chip significantly reduces the power consumption and improves the manufacturability of the decoder. This chip has general application in the implementation of high speed Viterbi decoders

The design and implementation of a microprocessor controlled adaptive filter

This thesis describes the construction and implementation of a microprocessor controlled recursive adaptive filter applied as a noise canceller. It describes the concept of the adaptive noise canceller, a method of estimating the received signal corrupted with additive interference (noise). This canceller has two inputs, the primary input containing the corrupted signal and the reference input consisting of the additive noise correlated in some unknown way to the primary noise. The reference input is filtered and subtracted from the primary input without degrading the desired components of the signal. This filtering process is adaptive and based on Widrow-Hoff Least-Mean-Square algorithm. Adaptive filters are programmable and have the capability to adjust their own parameters in situations where minimum piori knowledge is available about the inputs. For recursive filters, these parameters include feed-forward (non-recursive) as well as feedback (recursive) coefficients. A new design and implementation of the adaptive filter is suggested which uses a high speed 68000 microprocessor to accomplish the coefficients updating operation. Many practical problems arising in the hardware implementation are investigated. Simulation results illustrate the ability of the adaptive noise canceller to have an acceptable performance when the coefficients updating operation is carried out once every N sampling periods. Both simulation and hardware experimental results are in agreement

Study of numeric Saturation Effects in Linear Digital Compensators

Saturation arithmetic is often used in finite precision digital compensators to circumvent instability due to radix overflow. The saturation limits in the digital structure lead to nonlinear behavior during large state transients. It is shown that if all recursive loops in a compensator are interrupted by at least one saturation limit, then there exists a bounded external scaling rule which assures against overflow at all nodes in the structure. Design methods are proposed based on the generalized second method of Lyapunov, which take the internal saturation limits into account to implement a robust dual-mode suboptimal control for bounded input plants. The saturating digital compensator provides linear regulation for small disturbances, and near-time-optimal control for large disturbances or changes in the operating point. Computer aided design tools are developed to facilitate the analysis and design of this class of digital compensators

Real-time filtering and detection of dynamics for compression of HDTV

The preprocessing of video sequences for data compressing is discussed. The end goal associated with this is a compression system for HDTV capable of transmitting perceptually lossless sequences at under one bit per pixel. Two subtopics were emphasized to prepare the video signal for more efficient coding: (1) nonlinear filtering to remove noise and shape the signal spectrum to take advantage of insensitivities of human viewers; and (2) segmentation of each frame into temporally dynamic/static regions for conditional frame replenishment. The latter technique operates best under the assumption that the sequence can be modelled as a superposition of active foreground and static background. The considerations were restricted to monochrome data, since it was expected to use the standard luminance/chrominance decomposition, which concentrates most of the bandwidth requirements in the luminance. Similar methods may be applied to the two chrominance signals

Novel Front-end Electronics for Time Projection Chamber Detectors

Este trabajo ha sido realizado en la Organización Europea para la Investigación Nuclear (CERN) y forma parte del proyecto de investigación Europeo para futuros aceleradores lineales (EUDET). En física de partículas existen diferentes categorías de detectores de partículas. El diseño presentado esta centrado en un tipo particular de detector de trayectoria de partículas denominado TPC (Time Projection Chamber) que proporciona una imagen en tres dimensiones de las partículas eléctricamente cargadas que atraviesan su volumen gaseoso. La tesis incluye un estudio de los objetivos para futuros detectores, resumiendo los parámetros que un sistema de adquisición de datos debe cumplir en esos casos. Además, estos requisitos son comparados con los actuales sistemas de lectura utilizados en diferentes detectores TPC. Se concluye que ninguno de los sistemas cumple las restrictivas condiciones. Algunos de los principales objetivos para futuros detectores TPC son un altísimo nivel de integración, incremento del número de canales, electrónica más rápida y muy baja potencia. El principal inconveniente del estado del arte de los sistemas anteriores es la utilización de varios circuitos integrados en la cadena de adquisición. Este hecho hace imposible alcanzar el altísimo nivel de integración requerido para futuros detectores. Además, un aumento del número de canales y frecuencia de muestreo haría incrementar hasta valores no permitidos la potencia utilizada. Y en consecuencia, incrementar la refrigeración necesaria (en caso de ser posible). Una de las novedades presentadas es la integración de toda la cadena de adquisición (filtros analógicos de entrada, conversor analógico-digital (ADC) y procesado de señal digital) en un único circuito integrado en tecnología de 130nm. Este chip es el primero que realiza esta altísima integración para detectores TPC. Por otro lado, se presenta un análisis detallado de los filtros de procesado de señal. Los objetivos más importantes es la reduccióGarcía García, EJ. (2012). Novel Front-end Electronics for Time Projection Chamber Detectors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/16980Palanci

Concepts in LSI servo-control-electronics

This thesis deals with the engineering aspects of control electronics. It examines modern concepts of servo-control theory in the light of recent developments in the technology of monolithic circuits. Applicational considerations are slanted towards Aerospace standards of reliability and power-consumption economy. Conclusions drawn from the discussion of fabrication constraints and performance requirements lead to a preference for digital implementations. Yield problems on one hand and aging effects on the other greatly reduce the feasibility rating of analog arrays. Current practice in servo-control electronics revolves around purely analog implementations, sampled-data systems and Primitive on-off arrangements. The motivation behind the status quo and the justification of the proposed approach are discussed in detail. The organization of digital systems is examined in order to demonstrate the feasibility of Large Scale Integration (LSI) in servo-control electronics. The questions of hardware versatility and power-dissipation economy are emphasized from technological, economical and applicational standpoints. Self-Contained loops and Computer-Aided systems investigated within the ramifications of a functional division into Detectors, Compensators and Drivers. Differential Frequency Modulation is assumed to effect the information transfer from the Pick-Off coil of the transducer to tie input ports of the Ratemeter. Pulse Width-Frequency Modulation is employed at the Driver-Torquer interface. The operation of the Ratameter conforms with classical logic, except for a slope-independent Level-Crossing-Discriminator (LCD), which is designed to provide a time-resolution gain of 3 db. over conventional frequency detectors. Circuit detais of the LCD are given in order to illustrate differences between integrated and discrete circuit configurations. Two types of compensators are discussed: canonic pole-zero arrangements with ROM multipliers and Kalman fiiters with stored-program implementations of covariance equations. The concept of Pulse-Width-Frequency-Modulation (PWFM) is introduced co reconcile the dynamic-range requirements or servo-control drivers with the time-resolution limitations of power transistors. Simple means of implementation of PWFM are also given; they take the form. of a combination of logic-gates and DDA elements, a technique which could be used to advantage in other applications, especially digital detection and filtration