A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

A pll based frequency synthesizer in 0.13 um sige bicmos for mb-ofdm uwb systems

With the growing demand for high-speed and high-quality short-range communication, multi-band orthogonal frequency division multiplexing ultra-wide band (MB-OFDM UWB) systems have recently garnered considerable interest in industry and in academia. To achieve a low-cost solution, highly integrated transceivers with small die area and minimum power consumption are required. The key building block of the transceiver is the frequency synthesizer. A frequency synthesizer comprised of two PLLs and one multiplexer is presented in this thesis. Ring oscillators are adopted for PLL implementation in order to drastically reduce the die area of the frequency synthesizer. The poor spectral purity appearing in the frequency synthesizers involving mixers is greatly improved in this design. Based on the specifications derived from application standards, a design methodology is presented to obtain the parameters of building blocks. As well, the simulation results are provided to verify the performance of proposed design

Modular platform for research in microgrids

The present Ph.D. thesis has been developed following an Industrial Ph.D. program and verses on developing a commercial piece of equipment for teknoCEA, a spin-off company from CITCEA-UPC. The thesis is centered on developing power electronics-based emulation systems for research in microgrids. Lately, the use of power electronics-based emulation systems is drawing substantial attention in the field of microgrids because their characteristics substantially facilitate research in laboratory facilities. First, the suitability of different topologies for implementing an emulation platform is analyzed. The focus is set on the topologies adjustability to implement various types of emulation systems. The analysis determines the most appropriate number of legs for the platform. A comparative analysis is done between two-level and multi-level topologies to determine their suitability based on different aspects. Moreover, the analysis confirms the usefulness of wide-bandgap semiconductors for this type of application. Next, a control structure is proposed together with its implementation in a low-cost microcontroller based on a modular software architecture. The control strategy based on fractional proportional resonant controllers for AC emulation systems provides a control system with high control bandwidth while keeping a low computational cost. The control strategy for DC emulation systems is provided to reach a fast transient response and immunity to external disturbances, which is key for good emulation of electric systems. The modular software architecture provides a software framework easily adjustable to the needs of multiple emulation systems. That allows the implementation of the multiple control strategies with minimum changes. Additionally provides a graphical representation of the software architecture from a static and dynamic point of view. Last, the reliability of the proposed platform is assessed based on the reliability curves provided in the literature. The reliability analysis is centered on the semiconductors and capacitors. It provides evidence that emulation systems typical currents and voltages clearly affect their reliability. For the capacitors reliability assessment, a thermal modeling methodology is proposed to overcome the limitations of standard approximations. The methodology is based on anisotropic modeling of the capacitor winding. Finally, the reliability analysis establishes the guidelines to assess the platform reliability if a given mission profile is provided.La present tesi doctoral s'ha dut a terme seguint un programa de doctorat industrial. La tesi exposa el desenvolupament d'un equip comercial per a teknoCEA, una spin-off del CITCEA-UPC. La tesi es centra en el desenvolupament d'emuladors basats en electrònica de potència per recerca en el camp de les microxarxes. Darrerament, l'ús d'emuladors s'ha estès ja que les seves característiques faciliten molt la recerca en laboratoris. En primer lloc, s'analitza la idoneïtat de diferents topologies per implementar una plataforma d'emulació. El focus recau en la capacitat de diferents topologies per ajustar-se a la implementació de múltiples sistemes d'emulació. L'anàlisi determina el número òptim de branques. Un anàlisi comparatiu entre topologies dos nivells i multinivell permet determinar-ne la idoneïtat en funció de diferents aspectes. A continuació, es proposa una estructura de control juntament amb la seva implementació en un microcontrolador de baix cost a partir d'una arquitectura de programari modular. L'estratègia de control basada en controladors FPR (fractional proportional resonant) per a emuladors de corrent altern, proporciona un sistema de control amb un gran ample de banda amb un baix cost computacional. L'estratègia de control proposada per emuladors de corrent continu proporciona una resposta transitòria ràpida i elevada immunitat a pertorbacions, aspecte clau per a una bona emulació de sistemes elèctrics. L'arquitectura de programari modular proporciona un marc de programari fàcilment ajustable a les necessitats de múltiples emuladors. Això permet la implementació de les múltiples estratègies de control amb canvis mínims. A més, ofereix una representació gràfica de l'arquitectura del programari tant des d'un punt de vista estàtic com dinàmic. Finalment, s'avalua la fiabilitat de la plataforma a partir de les corbes de fiabilitat disponibles a la bibliografia científica. L'anàlisi es centra en els semiconductors i condensadors i proporciona evidència que els corrents i les tensions típics en emuladors afecten la seva fiabilitat. Per a l'avaluació de la fiabilitat dels condensadors, es proposa una metodologia de modelització tèrmica que permet superar les limitacions de les metodologies emprades típicament en la bibliografia científica. La metodologia es basa en el modelatge del bobinat del condensador com un element anisòtrop. Per últim, l'anàlisi de fiabilitat estableix les pautes per avaluar la fiabilitat de la plataforma en el cas que es proporcioni un perfil d'operació determinat.Postprint (published version

Low-power CMOS digital-pixel Imagers for high-speed uncooled PbSe IR applications

This PhD dissertation describes the research and development of a new low-cost medium wavelength infrared MWIR monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapour phase deposition (VPD) PbSe-based medium wavelength IR (MWIR) detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. The work supports on the hypothesis that, by the use of the preceding design techniques, current standard inexpensive CMOS technologies fulfill all operational requirements of the VPD PbSe detector in terms of connectivity, reliability, functionality and scalability to integrate the device. The resulting monolithic PbSe-CMOS camera must consume very low power, operate at kHz frequencies, exhibit good uniformity and fit the CMOS read-out active pixels in the compact pitch of the focal plane, all while addressing the particular characteristics of the MWIR detector: high dark-to-signal ratios, large input parasitic capacitance values and remarkable mismatching in PbSe integration. In order to achieve these demands, this thesis proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation. The main aim is to potentiate the integration of PbSe-based infra-red (IR)-image sensing technologies so as to widen its use, not only in distinct scenarios, but also at different stages of PbSe-CMOS integration maturity. For this purpose, we posit to investigate a comprehensive set of functional blocks distributed in two parallel approaches: • Frame-based “Smart” MWIR imaging based on new DPS circuit topologies with gain and offset FPN correction capabilities. This research line exploits the detector pitch to offer fully-digital programmability at pixel level and complete functionality with input parasitic capacitance compensation and internal frame memory. • Frame-free “Compact”-pitch MWIR vision based on a novel DPS lossless analog integrator and configurable temporal difference, combined with asynchronous communication protocols inside the focal plane. This strategy is conceived to allow extensive pitch compaction and readout speed increase by the suppression of in-pixel digital filtering, and the use of dynamic bandwidth allocation in each pixel of the FPA. In order make the electrical validation of first prototypes independent of the expensive PbSe deposition processes at wafer level, investigation is extended as well to the development of affordable sensor emulation strategies and integrated test platforms specifically oriented to image read-out integrated circuits. DPS cells, imagers and test chips have been fabricated and characterized in standard 0.15μm 1P6M, 0.35μm 2P4M and 2.5μm 2P1M CMOS technologies, all as part of research projects with industrial partnership. The research has led to the first high-speed uncooled frame-based IR quantum imager monolithically fabricated in a standard VLSI CMOS technology, and has given rise to the Tachyon series [1], a new line of commercial IR cameras used in real-time industrial, environmental and transportation control systems. The frame-free architectures investigated in this work represent a firm step forward to push further pixel pitch and system bandwidth up to the limits imposed by the evolving PbSe detector in future generations of the device.La present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat. Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació. Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar. L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: - Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma. - Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Per tal d'independitzar la validació elèctrica dels primers prototips respecte a costosos processos de deposició del PbSe sensor a nivell d'oblia, la recerca s'amplia també al desenvolupament de noves estratègies d'emulació del detector d'IR i plataformes de test integrades especialment orientades a circuits integrats de lectura d'imatge. Cel·les DPS, dispositius d'imatge i xips de test s'han fabricat i caracteritzat, respectivament, en tecnologies CMOS estàndard 0.15 micres 1P6M, 0.35 micres 2P4M i 2.5 micres 2P1M, tots dins el marc de projectes de recerca amb socis industrials. Aquest treball ha conduït a la fabricació del primer dispositiu quàntic d'imatgeria IR d'alta velocitat, no refrigerat, basat en frames, i monolíticament fabricat en tecnologia VLSI CMOS estàndard, i ha donat lloc a Tachyon, una nova línia de càmeres IR comercials emprades en sistemes de control industrial, mediambiental i de transport en temps real.Postprint (published version

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

Power Management ICs for Internet of Things, Energy Harvesting and Biomedical Devices

This dissertation focuses on the power management unit (PMU) and integrated circuits (ICs) for the internet of things (IoT), energy harvesting and biomedical devices. Three monolithic power harvesting methods are studied for different challenges of smart nodes of IoT networks. Firstly, we propose that an impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption. Secondly, we develop a hill-climbing MPPT mechanism that reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Furthermore, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations as low as 12 µW. Thirdly, we introduce a reconfigurable charge pump to provide the hybrid conversion ratios (CRs) as 1⅓× up to 8× for minimizing the charge redistribution loss. The reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened across a wide harvesting range as 0.45 to 3 V. In a conclusion, we successfully develop an energy harvesting method for the IoT smart nodes with lower cost, smaller size, higher conversion efficiency, and better applicability. For the biomedical devices, this dissertation presents a novel cost-effective automatic resonance tracking method with maximum power transfer (MPT) for piezoelectric transducers (PT). The proposed tracking method is based on a band-pass filter (BPF) oscillator, exploiting the PT’s intrinsic resonance point through a sensing bridge. It guarantees automatic resonance tracking and maximum electrical power converted into mechanical motion regardless of process variations and environmental interferences. Thus, the proposed BPF oscillator-based scheme was designed for an ultrasonic vessel sealing and dissecting (UVSD) system. The sealing and dissecting functions were verified experimentally in chicken tissue and glycerin. Furthermore, a combined sensing scheme circuit allows multiple surgical tissue debulking, vessel sealer and dissector (VSD) technologies to operate from the same sensing scheme board. Its advantage is that a single driver controller could be used for both systems simplifying the complexity and design cost. In a conclusion, we successfully develop an ultrasonic scalpel to replace the other electrosurgical counterparts and the conventional scalpels with lower cost and better functionality

Ultra-low power radio transceiver for wireless sensor networks

The objective of this thesis is to present the design and implementation of ultra-low power radio transceivers at microwave frequencies, which are applicable to wireless sensor network (WSN) and, in particular, to the requirement of the Speckled Computing Consortium (or SpeckNet). This was achieved through quasi-MMIC prototypes and monolithic microwave integrated circuit (MMIC) with dc power consumption of less than 1mW and radio communication ranges operating at least one metre. A wireless sensor network is made up of widely distributed autonomous devices incorporating sensors to cooperatively monitor physical environments. There are different kinds of sensor network applications in which sensors perform a wide range of activities. Among these, a certain set of applications require that sensor nodes collect information about the physical environment. Each sensor node operates autonomously without a central node of control. However, there are many implementation challenges associated with sensor nodes. These nodes must consume extremely low power and must communicate with their neighbours at bit-rates in the order of hundreds of kilobits per second and potentially need to operate at high volumetric densities. Since the power constraint is the most challenging requirement, the radio transceiver must consume ultra-low power in order to prolong the limited battery capacity of a node. The radio transceiver must also be compact, less than 5×5 mm2, to achieve a target size for sensor node and operate over a range of at least one metre to allow communication between widely deployed nodes. Different transceiver topologies are discussed to choose the radio transceiver architecture with specifications that are required in this project. The conventional heterodyne and homodyne topologies are discussed to be unsuitable methods to achieve low power transceiver due to power hungry circuits and their high complexity. The super-regenerative transceiver is also discussed to be unsuitable method because it has a drawback of inherent frequency instability and its characteristics strongly depend on the performance of the super-regenerative oscillator. Instead, a more efficient method of modulation and demodulation such as on-off keying (OOK) is presented. Furthermore, design considerations are shown which can be used to achieve relatively large output voltages for small input powers using an OOK modulation system. This is important because transceiver does not require the use of additional circuits to increase gain or sensitivity and consequently it achieves lower power consumption in a sensor node. This thesis details the circuit design with both a commercial and in-house device technology with ultra-low dc power consumption while retaining adequate RF performance. It details the design of radio building blocks including amplifiers, oscillators, switches and detectors. Furthermore, the circuit integration is presented to achieve a compact transceiver and different circuit topologies to minimize dc power consumption are described. To achieve the sensitivity requirements of receiver, a detector design method with large output voltage is presented. The receiver is measured to have output voltages of 1mVp-p for input powers of -60dBm over a 1 metre operating range while consuming as much as 420μW. The first prototype combines all required blocks using an in-house GaAs MMIC process with commercial pseudomorphic high electron mobility transistor (PHEMT). The OOK radio transceiver successfully operates at the centre frequency of 10GHz for compact antenna and with ultra-low power consumption and shows an output power of -10.4dBm for the transmitter, an output voltage of 1mVp-p at an operating range of 1 metre for the receiver and a total power consumption of 840μW. Based on this prototype, an MMIC radio transceiver at the 24GHz band is also designed to further improve the performance and reduce the physical size with an advanced 50nm gate-length GaAs metamorphic high electron mobility transistor (MHEMT) device technology

Nanopower CMOS transponders for UHF and microwave RFID systems

At first, we present an analysis and a discussion of the design options and tradeoffs for a passive microwave transponder. We derive a set of criteria for the optimization of the voltage multiplier, the power matching network and the backscatter modulator in order to optimize the operating range. In order to match the strictly power requirements, the communication protocol between transponder and reader has been chosen in a convenient way, in order to make the architecture of the passive transponder very simple and then ultra-low-power. From the circuital point of view, the digital section has been implemented in subthreshold CMOS logic with very low supply voltage and clock frequency. We present different solutions to supply power to the transponder, in order to keep the power consumption in the deep sub-µW regime and to drastically reduce the huge sensitivity of the subthreshold logic to temperature and process variations. Moreover, a low-voltage and low-power EEPROM in a standard CMOS process has been implemented. Finally, we have presented the implementation of the entire passive transponder, operating in the UHF or microwave frequency range