Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Advanced Electrical Characterization of Oxide TFTs Design of a Temperature Compensated Voltage Reference

Any electronic device, regardless of its function, needs a reference voltage source that feeds reliably, i.e., which generates a constant voltage, upstream and regardless of external environmental conditions, such as temperature. Since such a characteristic negatively influences the behavior of the devices, whose base elements are transistors, it is essential to design a circuit that provides a voltage which is invariant over a temperature range. In this work is designed a circuit that is responsible for generating a reference voltage using only thin film transistors or TFTs, on glass substrate. However, in order to validate the concept used in the mentioned transistors, it is also dimensioned and simulated the proposed circuit in 130 nm CMOS technology, where the respective results are expected to be comparative between the two technologies. For CMOS technology, for a nominal reference voltage of 124,0 mV, Cadence simulation reveals ±2,2 ppm/ºC temperature coefficient, between -20 °C and 100 °C. The power consumptions are and 1,434 mW and 4,566 mW for both CMOS and IGZO-TFT technologies, respectively

Local Epitaxial Overgrowth for Stacked Complementary MOS Transistor Pairs

A three-dimensional silicon processing technology for CMOS circuits was developed and characterized. The first fully depleted SOI devices with individually biasable gates on both sides of the silicon film were realized. A vertically stacked CMOS Inverter built by lateral overgrowth was reported for the first time. Nucleation-free epitaxial lateral overgrowth of silicon over thin oxides was developed for both a pancake and a barrel-type epitaxy reactor: This process was optimized to limit damage to gate oxides and minimize dopant diffusion within the Substrate. Autodoping from impurities of the MOS transistors built in the substrate was greatly reduced. A planarisation technique was developed to reduce the silicon film thickness from 13μm to below 0.5μm for full depletion. Chemo-mechanical polishing was modified to yield an automatic etch stop with the corresponding control and uniformity of the silicon film. The resulting wafer topography is more planar than in a conventional substrate CMOS process. PMOS transistors which match the current drive of bulk NM0S devices of equal geometry were characterized, despite the three-times lower hole mobility. Devices realized in the substrate, at the bottom and on top of the SOI film were essentially indistinguishable from bulk devices. A novel device with two insulated gates controlling the same channel was characterized. Inverters were realized both as joint-gate configuration and with symmetric performance of n- and p-channel. These circuits were realized in the area of a single NMOS transistor

Energy- and Area-Efficient DC-DC Converters Fabricated in Low Temperature Crystalline Silicon-on-Glass Technology

The display industry is moving toward the development of system-on-panel (SOP) architectures to make increasingly compact small-format displays and reduce manufacturing cost. Presently, the voltages required by pixel drivers, row scan logic, and timing circuitry, are generated from a single supply voltage using charge pumps fabricated on a high voltage, monolithic integrated circuit mounted off the glass panel. In this work, a new high-efficiency charge pump architecture for fabrication on display glass substrates is presented. The distinguishing feature of this work is the nestedclock timing scheme used to improve power efficiency and reduce output voltage noise without the use of external capacitors. The circuit is intended for implementation on a novel low-temperature crystalline silicon thin-film transistor technology (SiOG) that exhibits superior performance compared to other low-temperature fabrication processes. Based on simulation results, the proposed circuit exhibits both smaller ripple voltage (61% smaller) and improved power efficiency (80.6% vs. 67.8%) when compared to previous work

Wide Bandwidth - High Accuracy Control Loops in the presence of Slow Varying Signals and Applications in Active Matrix Organic Light Emitting Displays and Sensor Arrays

This dissertation deals with the problems of modern active matrix organic light-emitting diode AMOLED display back-plane drivers and sensor arrays. The research described here, aims to classify recently utilized compensation techniques into distinct groups and further pinpoint their advantages and shortcomings. Additionally, a way of describing the loops as mathematical constructs is utilized to derive new circuits from the analog design perspective. A novel principle on display driving is derived by observing those mathematical control loop models and it is analyzed and evaluated as a novel way of pixel driving. Specifically, a new feedback current programming architecture and method is described and validated through experiments, which is compatible with AMOLED displays having the two transistor one capacitor (2T1C) pixel structure. The new pixel programming approach is compatible with all TFT technologies and can compensate for non-uniformities in both threshold voltage and carrier mobility of the pixel OLED drive TFT. Data gathered show that a pixel drive current of 20 nA can be programmed in less than 10usec. This new approach can be implemented within an AMOLED external or integrated display data driver. The method to achieve robustness in the operation of the loop is also presented here, observed through a series of measurements. All the peripheral blocks implementing the design are presented and analyzed through simulations and verified experimentally. Sources of noise are identified and eliminated, while new techniques for better isolation from digital noise are described and tested on a newly fabricated driver. Multiple versions of the new proposed circuit are outlined, simulated, fabricated and measured to evaluate their performance.A novel active matrix array approach suitable for a compact multi-channel gas sensor platform is also described. The proposed active matrix sensor array utilizes an array of P-i-N diodes each connected in series with an Inter-Digitated Electrode (IDE). The functionality of 8x8 and 16x16 sensor arrays measured through external current feedback loops is also presented for the 8x8 arrays and the detection of ammonia (NH3) and chlorine (Cl2) vapor sources is demonstrated

Crosstalk computing: circuit techniques, implementation and potential applications

Title from PDF of title [age viewed January 32, 2022Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 117-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2020This work presents a radically new computing concept for digital Integrated Circuits (ICs), called Crosstalk Computing. The conventional CMOS scaling trend is facing device scaling limitations and interconnect bottleneck. The other primary concern of miniaturization of ICs is the signal-integrity issue due to Crosstalk, which is the unwanted interference of signals between neighboring metal lines. The Crosstalk is becoming inexorable with advancing technology nodes. Traditional computing circuits always tries to reduce this Crosstalk by applying various circuit and layout techniques. In contrast, this research develops novel circuit techniques that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. This research work presents a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model. Along with regular digital logic circuits, it also presents a novel Polymorphic circuit approach unique to Crosstalk Computing. In Polymorphic circuits, the functionality of a circuit can be altered using a control variable. Owing to the multi-functional embodiment in polymorphic-circuits, they find many useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. This dissertation shows a comprehensive list of polymorphic logic gate implementations, which were not reported previously in any other work. It also performs a comparison study between Crosstalk polymorphic circuits and existing polymorphic approaches, which are either inefficient due to custom non-linear circuit styles or propose exotic devices. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation and characterization results show a 6x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in performance compared to counterpart implementation in CMOS circuit style. Nevertheless, the Crosstalk circuits also face issues while cascading the circuits; this research analyzes all the problems and develops auxiliary circuit techniques to fix the problems. Moreover, it shows a module-level cascaded polymorphic circuit example, which also employs the auxiliary circuit techniques developed. For the very first time, it implements a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65nm technology and demonstrates experimental evidence for runtime reconfiguration of the polymorphic circuit. The dissertation also explores the application potentials for Crosstalk Computing circuits. Finally, the future work section discusses the Electronic Design Automation (EDA) challenges and proposes an appropriate design flow; besides, it also discusses ideas for the efficient implementation of Crosstalk Computing structures. Thus, further research and development to realize efficient Crosstalk Computing structures can leverage the comprehensive circuit framework developed in this research and offer transformative benefits for the semiconductor industry.Introduction and Motivation -- More Moore and Relevant Beyond CMOS Research Directions -- Crosstalk Computing -- Crosstalk Circuits Based on Perception Model -- Crosstalk Circuit Types -- Cascading Circuit Issues and Sollutions -- Existing Polymorphic Circuit Approaches -- Crosstalk Polymorphic Circuits -- Comparison and Benchmarking of Crosstalk Gates -- Practical Realization of Crosstalk Gates -- Poential Applications -- Conclusion and Future Wor