The display industry is moving toward the development of system-on-panel (SOP) architectures to make increasingly compact small-format displays and reduce manufacturing cost. Presently, the voltages required by pixel drivers, row scan logic, and timing circuitry, are generated from a single supply voltage using charge pumps fabricated on a high voltage, monolithic integrated circuit mounted off the glass panel.
In this work, a new high-efficiency charge pump architecture for fabrication on display glass substrates is presented. The distinguishing feature of this work is the nestedclock timing scheme used to improve power efficiency and reduce output voltage noise without the use of external capacitors. The circuit is intended for implementation on a novel low-temperature crystalline silicon thin-film transistor technology (SiOG) that exhibits superior performance compared to other low-temperature fabrication processes. Based on simulation results, the proposed circuit exhibits both smaller ripple voltage (61% smaller) and improved power efficiency (80.6% vs. 67.8%) when compared to previous work
