43 research outputs found
Synthesis of asynchronous controllers using integer linear programming
A novel strategy for the logic synthesis of asynchronous control circuits is presented. It is based on the structural theory of Petri nets and integer linear programming. Techniques that are capable of checking implementability conditions, such as complete state coding, and deriving a gate netlist to implement the specified behavior are presented. These techniques can handle Petri net specifications consisting of several thousands of transitions and provide a significant speed-up compared with techniques that have previously been proposed.Peer ReviewedPostprint (published version
Interpreted graph models
A model class called an Interpreted Graph Model (IGM) is defined. This class includes a large number of graph-based models that are used in asynchronous circuit design and other applications of concurrecy. The defining characteristic of this model class is an underlying static graph-like structure where behavioural semantics are attached using additional entities, such as tokens or node/arc states. The similarities in notation and expressive power allow a number of operations on these formalisms, such as visualisation, interactive simulation, serialisation, schematic entry and model conversion to be generalised. A software framework called Workcraft was developed to take advantage of these properties of IGMs. Workcraft provides an environment for rapid prototyping of graph-like models and related tools. It provides a large set of standardised functions that considerably facilitate the task of providing tool support for any IGM. The concept of Interpreted Graph Models is the result of research on methods of application of lower level models, such as Petri nets, as a back-end for simulation and verification of higher level models that are more easily manipulated. The goal is to achieve a high degree of automation of this process. In particular, a method for verification of speed-independence of asynchronous circuits is presented. Using this method, the circuit is specified as a gate netlist and its environment is specified as a Signal Transition Graph. The circuit is then automatically translated into a behaviourally equivalent Petri net model. This model is then composed with the specification of the environment. A number of important properties can be established on this compound model, such as the absence of deadlocks and hazards. If a trace is found that violates the required property, it is automatically interpreted in terms of switching of the gates in the original gate-level circuit specification and may be presented visually to the circuit designer. A similar technique is also used for the verification of a model called Static Data Flow Structure (SDFS). This high level model describes the behaviour of an asynchronous data path. SDFS is particularly interesting because it models complex behaviours such as preemption, early evaluation and speculation. Preemption is a technique which allows to destroy data objects in a computation pipeline if the result of computation is no longer needed, reducing the power consumption. Early evaluation allows a circuit to compute the output using a subset of its inputs and preempting the inputs which are not needed. In speculation, all conflicting branches of computation run concurrently without waiting for the selecting condition; once the selecting condition is computed the unneeded branches are preempted. The automated Petri net based verification technique is especially useful in this case because of the complex nature of these features. As a result of this work, a number of cases are presented where the concept of IGMs and the Workcraft tool were instrumental. These include the design of two different types of arbiter circuits, the design and debugging of the SDFS model, synthesis of asynchronous circuits from the Conditional Partial Order Graph model and the modification of the workflow of Balsa asynchronous circuit synthesis system.EThOS - Electronic Theses Online ServiceEPSRCGBUnited Kingdo
Synthesis of timed circuits based on decomposition
Journal ArticleAbstract-This paper presents a decomposition-based method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed signal transition graph (STG) to include only transitions on the output of interest and its possible trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals, which must be reintroduced into the STG to obtain complete state coding. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full-state-space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool Nii-Utah Timed Asynchronous circuit Synthesis system (nutas), and its first version is available at http://research.nii.ac.jp/~yoneda
Automata-theoretic and bounded model checking for linear temporal logic
In this work we study methods for model checking the temporal logic LTL. The focus is on the automata-theoretic approach to model checking and bounded model checking.
We begin by examining automata-theoretic methods to model check LTL safety properties. The model checking problem can be reduced to checking whether the language of a finite state automaton on finite words is empty. We describe an efficient algorithm for generating small finite state automata for so called non-pathological safety properties. The presented implementation is the first tool able to decide whether a formula is non-pathological. The experimental results show that treating safety properties can benefit model checking at very little cost. In addition, we find supporting evidence for the view that minimising the automaton representing the property does not always lead to a small product state space. A deterministic property automaton can result in a smaller product state space even though it might have a larger number states.
Next we investigate modular analysis. Modular analysis is a state space reduction method for modular Petri nets. The method can be used to construct a reduced state space called the synchronisation graph. We devise an on-the-fly automata-theoretic method for model checking the behaviour of a modular Petri net from the synchronisation graph. The solution is based on reducing the model checking problem to an instance of verification with testers. We analyse the tester verification problem and present an efficient on-the-fly algorithm, the first complete solution to tester verification problem, based on generalised nested depth-first search.
We have also studied propositional encodings for bounded model checking LTL. A new simple linear sized encoding is developed and experimentally evaluated. The implementation in the NuSMV2 model checker is competitive with previously presented encodings. We show how to generalise the LTL encoding to a more succint logic: LTL with past operators. The generalised encoding compares favourably with previous encodings for LTL with past operators. Links between bounded model checking and the automata-theoretic approach are also explored.reviewe
Hardware synthesis from high-level scenario specifications
PhD ThesisThe behaviour of many systems can be partitioned into scenarios. These facilitate
engineers’ understanding of the specifications, and can be composed into efficient
implementations via a form of high-level synthesis. In this work, we focus on highly
concurrent systems, whose scenarios are typically described using concurrency models
such as partial orders, Petri nets and data-flow structures.
In this thesis, we study different aspects of hardware synthesis from high-level
scenario specifications. We propose new formal models to simplify the specification
of concurrent systems, and algorithms for hardware synthesis and verification of the
scenario-based models of such systems. We also propose solutions for mapping scenariobased
systems on silicon and evaluate their efficiency.
Our experiments show that the proposed approaches improve the design of concurrent
systems. The new formalisms can break down complex specifications into
significantly simpler scenarios automatically, and can be used to fully model the dataflow
of operations of reconfigurable event-driven systems. The proposed heuristics for
mapping the scenarios of a system to a digital circuit supports encoding constraints,
unlike existing methods, and can cope with specifications comprising hundreds of
scenarios at the cost of only 5% of area overhead compared to exact algorithms.
These experiments are driven by three case studies: (1) hardware synthesis of control
architectures, e.g. microprocessor control units; (2) acceleration of the ordinal pattern
encoding, i.e. an algorithm for detecting repetitive patterns within data streams; (3) and
acceleration of computational drug discovery, i.e. computation of shortest paths in large
protein-interaction networks.
Our findings are employed to design two prototypes, which have a practical value for
the considered case studies. The ordinal pattern encoding accelerator is asynchronous,
highly resilient to unstable voltage supply, and designed to perform a range of computations
via runtime reconfiguration. The drug discovery accelerator is synchronous, and
up to three orders of magnitude faster than conventional software implementations
Exploiting robustness in asynchronous circuits to design fine-tunable systems
PhD ThesisRobustness property in a circuit defines its tolerance to the effects of process, voltage and
temperature variations. The mode signaling and event communication between computing
units in a asynchronous circuits makes them inherently robust. The level of robustness
depends on the type of delay assumptions used in the design and specification process.
In this thesis, two approaches to exploiting robustness in asynchronous circuits to design
self-adapting and fine-tunable systems are investigated. In the first investigation, a Digitally
Controllable Oscillator (DCO) and a computing unit are integrated such that the operating
conditions of the computing unit modulated the operation of the DCO. In this investigation,
the computing unit which is a self-timed counter interacts with the DCO in a four-phase
handshake protocol. This mode of interaction ensures a DCO and computing unit system
that can fine-tune its operation to adapt to the effects of variations. In this investigation, it
is shown that such a system will operate correctly in wide range of voltage supply. In the
second investigation, a Digital Pulse-Width Modulator (DPWM) with coarse and fine-tune
controls is designed using two Kessels counters. The coarse control of the DPWM tuned the
pulse ratio and pulse frequency while the fine-tune control exploited the robustness property
of asynchronous circuits in an addition-based delay system to add or subtract delay(s) to
the pulse width while maintaining a constant pulse frequency. The DPWM realized gave
constant duty ratio regardless of the operating voltage. This type of DPWM has practical
application in a DC-DC converter circuit to tune the output voltage of the converter in high
resolution. The Kessels counter is a loadable self-timed modulo−n counter, which is realized
by decomposition using Horner’s method, specified and verified using formal asynchronous
design techniques. The decomposition method used introduced parallelism in the system by
dividing the counter into a systolic array of cells, with each cell further decomposed into
two parts that have distinct defined operations. Specification of the decomposed counter cell
parts operation was in three stages. The first stage employed high-level specification using
Labelled Petri nets (LPN). In this form, functional correctness of the decomposed counter is
modelled and verified. In the second stage, a cell part is specified by combing all possible
operations for that cell part in high-level form. With this approach, a combination of inputs
from a defined control block activated the correct operation for a cell part. In the final stage,
the LPNs were converted to Signal Transition Graphs, from which the logic circuits of the
cells were synthesized using the WorkCraft Tool. In this thesis, the Kessels counter was
implemented and fabricated in 350 nm CMOS Technology.Niger Delta Development Commission (NDD
Efficient symbolic model checking of concurrent systems
Design errors in software systems consisting of concurrent components are potentially disastrous, yet notoriously difficult to find by testing. Therefore, more rigorous analysis methods are gaining popularity. Symbolic model checking techniques are based on modeling the behavior of the system as a formula and reducing the analysis problem to symbolic manipulation of formulas by computational tools. In this work, the aim is to make symbolic model checking, in particular bounded model checking, more efficient for verifying and falsifying safety properties of highly concurrent system models with high-level data features.
The contributions of this thesis are divided to four topics. The first topic is symbolic model checking of UML state machine models. UML is a language widely used in the industry for modeling software-intensive systems. The contribution is an accurate semantics for a subset of the UML state machine language and an automatic translation to formulas, enabling symbolic UML model checking.
The second topic is bounded model checking of systems with queues. Queues are frequently used to model, for example, message buffers in distributed systems. The contribution is a variety of ways to encode the behavior of queues in formulas that exploit the features of modern SMT solver tools.
The third topic is symbolic partial order methods for accelerated model checking. By exploiting the inherent independence of the components of a concurrent system, the executions of the system are compressed by allowing several actions in different components to occur at the same time. Making the executions shorter increases the performance of bounded model checking. The contribution includes three alternative partial order semantics for compressing the executions, with analytic and experimental evaluation. The work also presents a new variant of bounded model checking that is based on a concurrent instead of sequential view of the events that constitute an execution.
The fourth topic is efficient computation of predicate abstraction. Predicate abstraction is a key technique for scalable model checking, based on replacing the system model by a simpler abstract model that omits irrelevant details. In practice, constructing the abstract model can be computationally expensive. The contribution is a combination of techniques that exploit the structure of the underlying system to partition the problem into a sequence of cheaper abstraction problems, thus reducing the total complexity
Power-compute co-design for robust pervasive IoT applications
PhD ThesisThe modern development of internet of things (IoT) requires the IoT devices to be more
compact and energy autonomous. Many of them require to be able to operate with
unstable and low power supplies that come from various energy sources such as energy
harvesters. This creates a challenge for building IoT devices that need to be robust to
energy variations.
In this research we propose methods for improving energy characteristics of IoT
devices from the perspective of two main challenges: (i) improving the efficiency
and stability of power regulators, and (ii) enhancing the energy robustness of the IoT
devices. The existing design methods do not consider these two aspects holistically. One
important feature of our approach is holistic use of event-based, temporal representation
of data, which involves using asynchronous techniques and duty-cycle-based encoding.
For power regulation we use switched-capacitor converters (SCC) because they offer
compactness and ease of on-chip implementation. In this research we adapt the existing
methods and develop new techniques for SCC design based on asynchronous circuits.
This allows us to improve their performance and stability. We also investigate the
methods of parasitic charge redistribution, and apply them to self-oscillating SCC,
improving their performance. The key contribution within (i) is development of the
methods of SCC design with improved characteristics.
The majority of novel IoT systems are shifting towards the “AI at the edge” vision,
for example, involving neural networks (NN). We consider a perceptron-based neural
network as a typical IoT computing device. In our research we propose a novel
NN design approach using the principle of pulse-width modulation (PWM). PWMencoded
signals represent information with their duty cycle values which may be made
independent of the voltages and frequencies of the carrier signals. As a result, the device
is more robust to voltage variations, and, thus, the power regulation can be simplified.
This is the second major contribution addressing challenge (ii).
The advantages of the proposed methods are validated with simulations in the
Cadence environment. The simulations demonstrate the operation of the designed
power regulators, and the improvements of their efficiency. The simulations also
demonstrate the principle of operation of the PWM-based perceptron and prove its
power and frequency elasticity.
The thesis gives future research directions into a deeper study of the holistic co-design
of a variation-robust power-compute paradigm and its impact on developing future IoT
applications