Towards a bio-inspired mixed-signal retinal processor

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A micropower centroiding vision processor

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A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits

Given the stringent requirements of energy efficiency for Internet-of-Things edge devices, approximate multipliers, as a basic component of many processors and accelerators, have been constantly proposed and studied for decades, especially in error-resilient applications. The computation error and energy efficiency largely depend on how and where the approximation is introduced into a design. Thus, this article aims to provide a comprehensive review of the approximation techniques in multiplier designs ranging from algorithms and architectures to circuits. We have implemented representative approximate multiplier designs in each category to understand the impact of the design techniques on accuracy and efficiency. The designs can then be effectively deployed in high-level applications, such as machine learning, to gain energy efficiency at the cost of slight accuracy loss.Comment: 38 pages, 37 figure

Design of Quaternary Logic Carry Look-Ahead Adder

In today's state-of-the-art VLSI technology, binary number system has been the choice for designing digital subsystems. Although technology development has made down scaling of devices possible, which in turn has resulted in a remarkable increase in density and functionality of VLSI systems, there are also significant drawbacks associated to the conventional binary number based system implementations. As the number of devices in VLSI circuits increases to billion of transistors in a chip area of , interconnection between the active devices both on chip and outside of a chip becomes considerably complicated. In a typical VLSI chip, about 70 percent of the chip area is occupied by interconnections whereas just 10 percent of the chip area is devoted to the devices and the remaining 20 percent is used for insulation. mm2 In this situation, multiple valued logics have attracted a considerable attention of researchers as a solution to overcome the above mentioned problem. Since fewer digits are required to represent a number in higher radices than in the binary number system, multiple valued logic circuits have the potential to minimize the number of interconnections. This thesis presents voltage-mode quaternary (4-valued) logic carry lookahead adder design using Silicon-On-Insulator (SOI) MOSFETs. The choice of adder subsystem is made because addition operation is the most frequently used operation in a general purpose system and in application specific processors. Further more, the other operations like subtraction, multiplication and division are based on addition operation of the arithmetic unit. In this study, an efficient logic to realize 4-valued logic addition operation is proposed. The presented method is in conjunction with binary logic concepts and is easily developed for look-ahead logic. Following the proposed method has resulted in logic circuits with shorter gate depth and faster speed of operation as compared to what the other researchers have proposed. To meet the design requirements of the proposed low-voltage low-power circuits, multiple threshold voltage SOI MOSFETs are used. This choice is made because of their capability to operate at low power supply voltages and their ability to remain at the adjusted threshold voltages while presenting better subthreshold characteristics compared to the bulk MOSFETs. The proposed half and full adder blocks are divided into a few subblocks which could be considered as primitive gates. Transistor-Resistor Logic is used to implement each of them. Spice simulations have been performed on the proposed logic subblocks and their transient behaviors have been studied. Finally, the propagation delay, power consumption and overall performance of the proposed circuits are compared with other adder circuits proposed by other researchers. The presented adder circuits in this work have shown up to 58% reduction in critical propagation delay and 20% less power dissipation resulting in 64% reduction in power-delay product in comparison with other reported work. When compared to the binary logic carry look-ahead adder using the same technology (SOI), 54.39% improvement in power dissipation was achieved

Number Systems for Deep Neural Network Architectures: A Survey

Deep neural networks (DNNs) have become an enabling component for a myriad of artificial intelligence applications. DNNs have shown sometimes superior performance, even compared to humans, in cases such as self-driving, health applications, etc. Because of their computational complexity, deploying DNNs in resource-constrained devices still faces many challenges related to computing complexity, energy efficiency, latency, and cost. To this end, several research directions are being pursued by both academia and industry to accelerate and efficiently implement DNNs. One important direction is determining the appropriate data representation for the massive amount of data involved in DNN processing. Using conventional number systems has been found to be sub-optimal for DNNs. Alternatively, a great body of research focuses on exploring suitable number systems. This article aims to provide a comprehensive survey and discussion about alternative number systems for more efficient representations of DNN data. Various number systems (conventional/unconventional) exploited for DNNs are discussed. The impact of these number systems on the performance and hardware design of DNNs is considered. In addition, this paper highlights the challenges associated with each number system and various solutions that are proposed for addressing them. The reader will be able to understand the importance of an efficient number system for DNN, learn about the widely used number systems for DNN, understand the trade-offs between various number systems, and consider various design aspects that affect the impact of number systems on DNN performance. In addition, the recent trends and related research opportunities will be highlightedComment: 28 page