Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

Three-dimensional (3D) stacking of integrated circuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconnects and accordingly the signal delay time. On the other hand, the ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities. Thus, the development of new chip cooling concepts is of utmost importance. Therefore, scalable cooling solutions for chip stacks, such as interlayer cooling, need to be investigated. This paper presents a new concept for the integration of intra chip stack fluidic cooling, namely die-embedded microchannels for single- and twophase thermal management, using a patterned thin-layer eutectic solder bonding technique for the stack assembly. Results showed the successful fabrication of 5-layer chip stacks with embedded microchannels and high aspect ratio TSVs. Optical inspections demonstrated the proper bond line formation and direct current (DC) daisy-chain electrical tests indicated the successful combination of TSVs with thin-layer solder interconnects. Mechanical shear tests on die-on-die bonded samples showed the strength of the patterned thin-layer solder bond (16MPa). An added solder ring-pad component to seal the electrically active pad from any conductive liquid coolant was also investigated and reflow tests on such geometries showed the appearance of a balling effect along the solder ring line. This balling was found to be mitigated when the ring aspect ratio (deposited solder height to ring width ratio) was kept below the experimentally observed critical value of 0.65

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs

A key challenge for three dimensional (3D) integrated circuits (ICs) is thermal management. There are two main thermal challenges in typical 3D ICs. First, in the homogeneous integration with multiple high-power tiers, an effective cooling solution that scales with the number of dice in the stack is needed. Second, in the heterogeneous integration, an effective thermal isolation solution is needed to ‘protect’ the low-power tier from the high-power tier. This research focuses to address these two thermal challenges through hybrid microfluidic cooling and thermal isolation technologies. Within-tier microfluidic cooling is proposed and demonstrated to cool a stack with multiple high-power tiers. Electrical thermal co-analysis is performed to understand the trade-offs between through silicon via (TSV) parasitics and heat sink performance. A TSV-compatible micropin-fin heat sink is designed, fabricated and thermally characterized in a single tier, and benchmarked with a conventional air-cooled heat sink. The designed heat sink has a thermal resistance of 0.269 K·cm2/W at a flow rate of 70 mL/min. High aspect ratios TSVs (18:1) are integrated in the micropin-fins. Within-tier microfluidic cooling is then implemented in 3D stacks to emulate different heating scenarios, such as memory-on-processor and processor-on-processor. Air gap and mechanically flexible interconnects (MFIs) are proposed for the first time to decrease the vertical thermal coupling between high-power (e.g. processor) and low-power tiers (e.g. memory or nanophotonics). A two-tier testbed with the proposed thermal isolation technology is designed, fabricated and tested. Compared with conventional 3D integration approach, thermal isolation technology helps reduce the temperature at a fixed location in the low-tier by 12.9 °C. The resistance of a single MFI is measured to be 46.49 mΩ.Ph.D

Development of the recess mounting with monolithic metallization optoelectronic integrated circuit technology for optical clock distribution applications

Thesis (Elec. E.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.Includes bibliographical references (p. 123-128).Recess mounting with monolithic metallization, or RM3 integration, is used to integrate Ino.47Ga0.53As/InP based lattice-matched high quantum efficiency p-i-n photodetectors on silicon chips to build high performance optoelectronic integrated circuits [1]. In RM3 integration, partially processed heterostructure devices are placed in recesses formed in the dielectric layers covering the surface of an integrated circuit chip, the surface is planarized, and monolithic processing is continued to transform the heterostructures into optoelectronic devices monolithically integrated with the underlying electronic circuitry. Two different RM3 techniques have been investigated, Aligned Pillar Bonding (APB) and OptoPill Assembly (OPA). APB integrates lattice mismatched materials using aligned, selective area wafer bonding at reduced temperature (under 3500C), which protects the electronic chips from the adverse effects of high temperatures, and reduces the thermal expansion mismatch concerns. In the OPA technique, optoelectronic heterostructures are processed into circular pills of 8 gm height and 45 gm diameter, the pills are released from the substrate, and collected through a process that involves decanting.(cont.) The pills are then assembled into recesses on silicon chips using manual pick & place techniques, and they are bonded to the metal pads on the bottom surface of the recesses using a Cu-AuSn solder bond. A new magnet assisted bonding technique is utilized to obtain clamping pressure to form the solder bond. The gap between the pill and the surrounding recess is filled using BCB, which also provides good surface planarization.by Eralp Atmaca.Elec.E

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Enabling Capillary Self-Assembly for Microsystem Integration

Efficient and precise assembly of very-large quantities of sub-millimeter-sized devices onto pre-processed substrates is presently a key frontier for microelectronics, in its aspiration to large-scale mass production of devices with new functionalities and applications (e.g. thin dies embedded into flexible substrates, 3D microsystem integration). In this perspective, on the one hand established pick&place assembly techniques may be unsuitable, due to a trade-off between throughput and placement accuracy and to difficulties in predictably handling very-small devices. On the other hand, self-assembly processes are massively parallel, may run unsupervised and allow contactless manipulation of objects. The convergence between robotic assembly and self-assembly, epitomized by capillarity-enhanced flip-chip assembly, can therefore enable an ideal technology meeting short-to-medium-term electronic packaging and assembly needs. The objective of this thesis is bridging the gap between academic proofs-of- concept of capillary self-assembly and its industrial application. Our work solves several issues relevant to capillary self-assembly of thin dies onto preprocessed substrates. Very-different phenomena and aspects of both scientific and technological interest coexist in such a broad context. They were tackled both experimentally and theoretically. After a critical review of the state-of-the-art in microsystem integration, a complete quasi-static study of lateral capillary meniscus forces is presented. Our experimental setup enables also a novel method to measure the contact angle of liquids. Recessed binding sites are introduced to obtain perfectly-conformal fluid dip-coating of patterned surfaces, which enables the effective and robust coding of geometrical information into binding sites to direct the assembly of parts. A general procedure to establish solder-mediated electro-mechanical interconnections between parts and substrate is validated. Smart surface chemistries are invoked to solve the issue of mutual adhesion between parts during the capillary self-assembly process. Two chemical kinetic-inspired analytic models of fluidic self-assembly are presented and criticized to introduce a novel agent-based model of the process. The latter approach allows realistic simulations by taking into account spatial factors and collision dynamics. Concluding speculations propose envisioned solutions to residual open issues and further perspectives for this field of rapidly-growing importance

LHCb VELO Upgrade: Technical Design Report

The upgraded LHCb VELO silicon vertex detector is a lightweight hybrid pixel detector capable of 40 MHz readout at a luminosity of 2×10^33 cm^−2 s^−1. The track reconstruction speed and precision is enhanced relative to the current VELO detector even at the high occupancy conditions of the upgrade, due to the pixel geometry and a closest distance of approach to the LHC beams of just 5.1 mm for the first sensitive pixel. Cooling is provided by evaporative CO2 circulating in microchannel cooling substrates. The detector contains 41 million 55μ×55μ pixels, read out by the custom developed VeloPix front end ASIC. The detector will start operation together with the rest of the upgraded LHCb experiment after the LHC LS2 shutdown, currently scheduled to end in 2019. This Technical Design Report describes the upgraded VELO system, planned construction and installation, and gives an overview of the expected detector performanc

Integration of optical interconnections and optoelectronic components in flexible substrates

Licht als informatiedrager voor datacommunicatie kende een ongezien succes in de laatste decennia. Wegens de lage verliezen en hoge datasnelheden hebben ze voor het overbruggen van lange afstanden hun elektrische tegenhangers reeds geruime tijd verdrongen. Deze trend zet zich ook voort voor korte afstand communicatie op printplaten. Naast zijn functie als informatiedrager, wordt licht ook gebruikt om een waaier aan fysische grootheden te meten. Ook hier heeft licht enkele significante voordelen t.o.v elektrische informatiedragers, waardoor optische sensoren wijdverspreid zijn. Een tweede duidelijke trend binnen de elektronica is het gebruik van flexibele printkaarten. Deze zijn veel dunner, lichter en betrouwbaarder dan de klassieke harde printkaarten, waardoor ze uiterst geschikt zijn voor draagbare toepassingen waar compactheid en een laag gewicht hoge vereisten zijn. De flexibiliteit van de printplaten laat ook toe hen te gebruiken op onvlakke oppervlakken en op bewegende onderdelen. Het doel van het gepresenteerde doctoraatswerk is de ontwikkeling van een nieuw technologieplatform dat bovengenoemde trends combineert. Alle bouwblokken van optische communicatie, gaande van actieve opto-elektronische componenten, aanstuurelektronica, golfgeleiderbaantjes en galvanische verbindingen tot optische koppelstructuren tussen de verschillende bouwblokken, worden zodanig gerealiseerd dat elke component flexibel is en geïntegreerd wordt in een dunne folie met een dikte van slechts 150µm. Op die manier bekomen we een flexibele folie met alle passieve en actieve onderdelen voor optische communicatie geïntegreerd met enkel een elektrische interface naar de buitenwereld, wat de aanvaarding en toepassing van deze technologie in de huidige elektronica aanzienlijk kan versnellen. Binnen het doctoraatswerk werden alle voorgestelde technologieën en processen gerealiseerd en geoptimaliseerd. Bovendien werden de optische verliezen, warmteaspecten, hoogfrequent gedrag, mechanisch gedrag en betrouwbaarheid van de technologie gekarakteriseerd en vergeleken met de huidige state-of-the-art

Design automation and analysis of three-dimensional integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 165-176).This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical interconnect, three-dimensional integration can achieve scalability and performance exceeding that of conventional fabrication technologies. There are two main contributions of this thesis. The first is a computer-aided design flow for the digital components of a three-dimensional integrated circuit (3-D IC). This flow primarily consists of two software tools: PR3D, a placement and routing tool for custom 3-D ICs based on standard cells, and 3-D Magic, a tool for designing, editing, and testing physical layout characteristics of 3-D ICs. The second contribution of this thesis is a performance analysis of the digital components of 3-D ICs. We use the above tools to determine the extent to which 3-D integration can improve timing, energy, and thermal performance. In doing so, we verify the estimates of stochastic computational models for 3-D IC interconnects and find that the models predict the optimal 3-D wire length to within 20% accuracy. We expand upon this analysis by examining how 3-D technology factors affect the optimal wire length that can be obtained. Our ultimate analysis extends this work by directly considering timing and energy in 3-D ICs. In all cases we find that significant performance improvements are possible. In contrast, thermal performance is expected to worsen with the use of 3-D integration. We examine precisely how thermal behavior scales in 3-D integration and determine quantitatively how the temperature may be controlled during the circuit placement process. We also show how advanced packaging(cont.) technologies may be leveraged to maintain acceptable die temperatures in 3-D ICs. Finally, we explore two issues for the future of 3-D integration. We determine how technology scaling impacts the effect of 3-D integration on circuit performance. We also consider how to improve the performance of digital components in a mixed-signal 3-D integrated circuit. We conclude with a look towards future 3-D IC design tools.by Shamik Das.Ph.D