Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

Analog Neural Programmable Optimizers in CMOS VLSI Technologies

A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial time-multiplexed general-purpose architecture is introduced for the real-time solution of this kind of problem in MOS VLSI. This architecture is a fully programmable and reconfigurable one exploiting SC techniques for the analog part and making extensive use of digital techniques for programmability

Application of Grey Wolf Optimizer Algorithm for Optimal Power Flow of Two-Terminal HVDC Transmission System

This paper applies a relatively new optimization method, the Grey Wolf Optimizer (GWO) algorithm for Optimal Power Flow (OPF) of twoterminal High Voltage Direct Current (HVDC) electrical power system. The OPF problem of pure AC power systems considers the minimization of total costs under equality and inequality constraints. Hence, the OPF problem of integrated AC-DC power systems is extended to incorporate HVDC links, while taking into consideration the power transfer control characteristics using a GWO algorithm. This algorithm is inspired by the hunting behavior and social leadership of grey wolves in nature. The proposed algorithm is applied to two different case-studies: the modified 5-bus and WSCC 9-bus test systems. The validity of the proposed algorithm is demonstrated by comparing the obtained results with those reported in literature using other optimization techniques. Analysis of the obtained results show that the proposed GWO algorithm is able to achieve shorter CPU time, as well as minimized total cost when compared with already existing optimization techniques. This conclusion proves the efficiency of the GWO algorithm

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Placement driven retiming with a coupled edge timing model

Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the predicted performance improvement will still be valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model taking into account the effect of retiming on capacitive loads of single wires as well as fanout systems. We propose the integration of retiming into a timing-driven standard cell placement environment based on simulated annealing. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on standard FEAS our approach achieved an improvement in cycle time of up to 34% and 17% on the average

Implementation Aspects of a Transmitted-Reference UWB Receiver

In this paper, we discuss the design issues of an ultra wide band (UWB) receiver targeting a single-chip CMOS implementation for low data-rate applications like ad hoc wireless sensor networks. A non-coherent transmitted reference (TR) receiver is chosen because of its small complexity compared to other architectures. After a brief recapitulation of the UWB fundamentals and a short discussion on the major differences between coherent and non-coherent receivers, we discuss issues, challenges and possible design solutions. Several simulation results obtained by means of a behavioral model are presented, together with an analysis of the trade-off between performance and complexity in an integrated circuit implementation