91 research outputs found
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs
Modern field programmable gate array(FPGA) can be partially dynamically
reconfigurable with heterogeneous resources distributed on the chip. And
FPGA-based partially dynamically reconfigurable system(FPGA-PDRS) can be used
to accelerate computing and improve computing flexibility.
However, the traditional design of FPGA-PDRS is based on manual design.
Implementing the automation of FPGA-PDRS needs to solve the problems of task
modules partitioning, scheduling, and floorplanning on heterogeneous resources.
Existing works only partly solve problems for the automation process of
FPGA-PDRS or model homogeneous resource for FPGA-PDRS.
To better solve the problems in the automation process of FPGA-PDRS and
narrow the gap between algorithm and application, in this paper, we propose a
complete workflow including three parts, pre-processing to generate the list of
task modules candidate shapes according to the resources requirements,
exploration process to search the solution of task modules partitioning,
scheduling, and floorplanning, and post-optimization to improve the success
rate of floorplan.
Experimental results show that, compared with state-of-the-art work, the
proposed complete workflow can improve performance by 18.7\%, reduce
communication cost by 8.6\%, on average, with improving the resources reuse
rate of the heterogeneous resources on the chip. And based on the solution
generated by the exploration process, the post-optimization can improve the
success rate of the floorplan by 14\%
Smart technologies for effective reconfiguration: the FASTER approach
Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows
The FASTER vision for designing dynamically reconfigurable systems
Extending product functionality and lifetime requires constant addition of new features to satisfy the growing customer needs and the evolving market and technology trends. software component adaptivity is straightforward but not enough: recent products include hardware accelerators for reasons of performance and power efficiency that also need to adapt to new requirements. Reconfigurable logic allows the definition of new functions to be implemented in dynamically instantiated hardware units, combining adaptivity with hardware speed and efficiency. For the Intrusion Detection System example, new rules can be hardcoded into the reconfigurable logic, achieving high performance, while providing the necessary adaptivity to new threats. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform combining a general purpose processor with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design- and run-time, the capabilities of partial dynamic reconfiguration. The FASTER project will facilitate the use of reconfigurable hardware by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology
RTRLIB : a high-level modeling tool for dynamically partially reconfigurable systems
Dissertação (mestrado)—Universidade de BrasÃlia, Faculdade de Tecnologia, Departamento de Engenharia Mecânica, 2020.Reconfiguração dinâmica parcial é considerada uma interessante técnica a ser aplicada para o
aumento da flexibilidade de sistemas implementados em FPGA, em função da implementação
dinâmica de módulos de hardware enquanto o restante do circuito permanece em operação. Trata-
se de uma técnica utilizada em sistemas com requisitos muito restritos, como adaptabilidade,
robustez, consumo de potência, custo e tolerância à falhas. Entretanto, a complexidade de desen-
volvimento de sistemas com reconfiguração dinâmica parcial é consideravelmente alta quando
comparada à de sistemas com lógica totalmente estática. Nesse sentido, novas metodologias e
ferramentas de desenvolvimento são necessárias para reduzir a complexidade de implementação
desse tipo de sistema.
Nesse contexto, esse trabalho apresenta o RTRLib, uma ferramenta de modelagem em alto
nÃvel para o desenvolvimento de sistemas com reconfiguração dinâmica parcial em dispositivos
Xilinx Zynq a partir da especificação e parametrização de alguns blocos. Sob condições especÃfi-
cas, o RTRLib automaticamante produz os scripts de hardware e software para implementação da
solução utilizando o Vivado Design Suite e o SDK. Tais scripts são compostos pelos comandos
necessários para a implementação do sistema desde a criação do projeto de hardware até a criação
do arquivo de boot. Uma vez que o RTRLib é composto por IP-Cores previamente caracterizados,
a ferramenta também pode ser utilizada para a análise, em fase de modelagem, do sistema a ser
implementado, por meio da estimação de caracterÃsticas importantes do sistema, como o consumo
de recursos e latência.
O presente trabalho também inclui novas funcionalidades implementadas no RTRLib no con-
texto do design de hardware e de software, como: generalização do script de hardware, mapea-
mento de IO, floorplanning por meio de uma GUI, criação de um gerador de script de software,
gerador de template de aplicação standalone que faz uso do partial reconfiguration controller
(PRC) e implementação de uma biblioteca para aplicações FreeRTOS.
Por fim, quatro estudos de casos foram implementados para demonstrar as funcionalidades da
ferramenta: um sistema de classificação de terrenos baseado em redes neurais, um sistema com
regressores lineares utilizado para controle de uma prótese miocinética de mão e, por último, uma
aplicação hipotética de um sistema com requisitos de tempo real.Partial dynamic reconfiguration is considered an interesting technique to increase flexibility in
FPGA designs due to the dynamic replacement of hardware modules while the remainder of the
circuit remains in operation. It is used in systems with hard requirements such as adaptability,
robustness, power consumption, cost, and fault-tolerance. However, the complexity to develop
dynamically partially reconfigurable systems in considerably higher comparing with static de-
signs. Therefore, new design methodologies and tools have been required to reduce the design
complexity of such systems.
In this context, this work presents the RTRLib, a high-level modeling tool for the development
of dynamically reconfigurable systems on Xilinx Zynq devices by a simple system specification
and parametrization of some blocks. Under specific conditions, RTRLib automatically generates
the hardware and software scripts to implement the solution using Vivado and SDK. These scripts
are composed by the sequential design steps from hardware project creation to the boot image
elaboration. Since RTRLib is composed of pre-characterized IP-Cores, the tool also can be used
to analyze the system behavior during the design process by the early estimation of essential
characteristics of the system such as resource consumption and latency.
The present work also includes the new functionalities implemented on RTRLib in the context
of the hardware and the software design, such as: hardware script generalization, IO mapping,
floorplanning by a GUI, software script creation, generator of a standalone template application
that uses PRC, and implementation of a FreeRTOS library application.
Finally, four case studies were implemented to demonstrate the tool capability: a system
for terrain classification based on neuron networks, a linear regressor system used to control a
myokinetic-based prosthetic hand, and a hypothetical real-time application
Embedded electronic systems driven by run-time reconfigurable hardware
Abstract
This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen
Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnologÃa hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando asà su implementación fÃsica –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnologÃa a través del prototipado de varias aplicaciones de ingenierÃa (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum
Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinà micament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinà mica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant aixà la seva implementació fÃsica –à rea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware està tic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria
Optimising and evaluating designs for reconfigurable hardware
Growing demand for computational performance, and the rising cost for chip design and
manufacturing make reconfigurable hardware increasingly attractive for digital system implementation.
Reconfigurable hardware, such as field-programmable gate arrays (FPGAs),
can deliver performance through parallelism while also providing flexibility to enable
application builders to reconfigure them. However, reconfigurable systems, particularly
those involving run-time reconfiguration, are often developed in an ad-hoc manner. Such
an approach usually results in low designer productivity and can lead to inefficient designs.
This thesis covers three main achievements that address this situation. The first
achievement is a model that captures design parameters of reconfigurable hardware and
performance parameters of a given application domain. This model supports optimisations
for several design metrics such as performance, area, and power consumption. The second
achievement is a technique that enhances the relocatability of bitstreams for reconfigurable
devices, taking into account heterogeneous resources. This method increases the flexibility
of modules represented by these bitstreams while reducing configuration storage size and
design compilation time. The third achievement is a technique to characterise the power
consumption of FPGAs in different activity modes. This technique includes the evaluation
of standby power and dedicated low-power modes, which are crucial in meeting the
requirements for battery-based mobile devices
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