A high speed serializer/deserializer design

A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in high speed SerDes design, which included the low jitter design, wide bandwidth design and low power design. A quarter-rate multiplexer/demultiplexer (MUX/DEMUX) was implemented. This quarter-rate structure decreases the required clock frequency from one half to one quarter of the data rate. It is shown that this significantly relaxes the design of the VCO at high speed and achieves lower power consumption. A novel multi-phase LC-ring oscillator was developed to supply a low noise clock to the SerDes. This proposed VCO combined an LC-tank with a ring structure to achieve both wide tuning range (11%) and low phase noise (-110dBc/Hz at 1MHz offset). With this structure, a data rate of 36 Gb/s was realized with a measured peak-to-peak jitter of 10ps using 0.18microm SiGe BiCMOS technology. The power consumption is 3.6W with 3.4V power supply voltage. At a 60 Gb/s data rate the simulated peak-to-peak jitter was 4.8ps using 65nm CMOS technology. The power consumption is 92mW with 2V power supply voltage. A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D process. Mismatches caused by the vertical tier-to-tier interconnections and the temperature influence in the 3D process were attenuated by the proposed calibration circuit. The design strategy and circuits developed from this dissertation provide significant benefit to both wired and wireless applications

Integrated Distributed Amplifiers for Ultra-Wideband BiCMOS Receivers Operating at Millimeter-Wave Frequencies

Millimetre-wave technology is used for applications such as telecommunications and imaging. For both applications, the bandwidth of existing systems has to be increased to support higher data rates and finer imaging resolutions. Millimetrewave circuits with very large bandwidths are developed in this thesis. The focus is put on amplifiers and the on-chip integration of the amplifiers with antennas. Circuit prototypes, fabricated in a commercially available 130nm Silicon-Germanium (SiGe) Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) process, validated the developed techniques. Cutting-edge performances have been achieved in the field of distributed and resonant-matched amplifiers, as well as in that of the antenna-amplifier co-integration. Examples are as follows: - A novel cascode gain-cell with three transistors was conceived. By means of transconductance peaking towards high frequencies, the losses of the synthetic line can be compensated up to higher frequencies. The properties were analytically derived and explained. Experimental demonstration validated the technique by a Traveling-Wave Amplifier (TWA) able to produce 10 dB of gain over a frequency band of 170GHz.# - Two Cascaded Single-Stage Distributed Amplifiers (CSSDAs) have been demonstrated. The first CSSDA, optimized for low power consumption, requires less than 20mW to provide 10 dB of gain over a frequency band of 130 GHz. The second amplifier was designed for high-frequency operation and works up to 250 GHz leading to a record bandwidth for distributed amplifiers in SiGe technology. - The first complete CSSDA circuit analysis as function of all key parameters was presented. The typical degradation of the CSSDA output matching towards high frequencies was analytically quantified. A balanced architecture was then introduced to retain the frequency-response advantages of CSSDAs and yet ensure matching over the frequency band of interested. A circuit prototype validated experimentally the technique. - The first traveling-wave power combiner and divider capable of operation from the MHz range up to 200 GHz were demonstrated. The circuits improved the state of the art of the maximum frequency of operation and the bandwidth by a factor of five. - A resonant-matched balanced amplifier was demonstrated with a centre frequency of 185 GHz, 10 dB of gain and a 55GHz wide –3 dB-bandwidth. The power consumption of the amplifier is 16.8mW, one of the lowest for this circuit class, while the bandwidth is the broadest reported in literature for resonant-matched amplifiers in SiGe technology

Highly Linear Filtering TIA for 5G wireless standard and beyond

The demand for high data rates in emerging wireless standards is a result of the growing number of wireless device subscribers. This demand is met by increasing the channel bandwidth in accordance with historical trends. As MIMO technology advances, more bands and antennas are expected to be used. The most recent 5G standard makes use of mm-wave bands above 24GHz to expand the channel bandwidth. Channel bandwidth can exceed 2GHz when carrier aggregation is used. From the receiver’s point of view, this makes the baseband filter’s design, which is often a TIA, more difficult. This is due to the fact that as the bandwidth approaches the GHz range, the TIA’s UGBW should be more than 5GHz and it should have a high loop gain up to high frequencies. A closed-loop TIA with configurable bandwidth up to 1.5GHz is described in this scenario. Operational Transconductance Amplifier (OTA) closed in shunt-feedback is the foundation of the TIA. The proposed OTA is based on FeedForward topology (FF) together with inductive peaking technique to ensure stability rather than using the traditional Miller compensation technique. The TIA is able to produce GLoop unity gain bandwidth of 7.5GHz and high loop gain (i.e. 27dB @ 1GHz) using this method. The mixer and LNA’s linearity will benefit from this. Utilizing TSMC 28nm CMOS technology, a prototype has been created using this methodology. The output integrated noise from 20MHz to 1.5GHz is lower than 300μVrms with a power consumption of 17mW, and the TIA achieves In-band OIP3 of 33dBm. Additionally, a direct-conversion receiver for 5G applications is described. The 7GHz RF signal is down-converted to baseband by the receiver. Two cascaded LNTAs based on a common-gate transformer-based design make up the frontend. With an RF gain of 80mS and a gain variability of 31dB, it provides wideband matching from 6GHz to 8GHz. A double-balanced passive mixer is driven by the LNTA. The channel bandwidth from 50MHz to 2GHz is covered by two baseband paths. The first path, called as the low frequency path (LF), covers the channel bandwidth ranging from 50MHz to 400 MHz. In contrast, the second path, called as the high frequency path (HF), covers the channel bandwidth between 800MHz and 2GHz. Two baseband provide gain variability of 14dB, making the overall receiver able to have a gain configurability from 45dB to 0dB. Out-of-band (OOB) selectivity at 4 times the band-edge is greater than 33dB for each configurability. When the gain is at its maximum, the noise figure is less than 5.8dB, and the slope of the noise rise as the gain falls is less than 0.7dB/dB. The receiver guarantee an IB-OIP3 larger than 21dBm for any gain configuration. The receiver has been implemented in TSMC 28nm CMOS technology, consuming 51mW for LF path and 68mW for HF path. The measurement results are in perfect accordance with the requirements of the design

A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap mixed-signal FFE in 55nm BiCMOS

Next generation high-speed wireline and optical communications will target single lane data rates over 200Gb/s. For this, the generation and transmission of >100 Gbaud PAM-4 is a key step. Recent transmitters in advanced CMOS and FinFET nodes [1,2] provide extensive transmit-side FFE capabilities at respectively 64 and 56Gbaud. Speed limitations in these technologies will make the transition to >100 Gbaud a challenge. Alternatively, InP-based multiplexers like [3] manage to reach >100 Gbaud easily. They also offer the possibility to create high-swing output drivers, necessary to efficiently drive optical modulators. However, InP solutions lack the ability to introduce more complex equalization of the signal. BiCMOS based transmitters like in [4], enable the integration of more complex circuits with respect to InP technologies, are capable to deliver high signal swings required for optical drivers and promise increased bandwidth compared to CMOS/FinFET. This paper presents a 120Gbaud PAM-4 TX incorporating a 7-tap FFE in a 55nm BiCMOS technology. The advantage of the presented FFE architecture is the efficient use of both digital and analog delay structures to obtain >100 Gbaud operation with a large amount of filter taps in a compact configuration

A Variable Bandwidth, Power-Scalable Optical Receiver Front-End

The tremendous growth in internet data traffic and computation power has increased demand for high-speed links in almost all communication systems. Normally, high-speed interconnects in a super computer are implemented using a short distance electrical medium such as a printed circuit board or coaxial cable. However, data transmission through an electrical medium suffers severe bandwidth limitation due to its distributed resistance, inductance and capacitance. To overcome this problem, several equalization techniques are adopted which can make the system more complex and power hungry. An efficient way to enhance the capacity of short-reach link is through the use of an optical channel rather than the band-limited electrical one. The analog front-end is the most important building block of the optical receiver as it converts the small current generated by the photodiode to a significant voltage level. In this work, we present an inductor-less, variable bandwidth, power-scalable optical receiver front-end in TSMC 65nm and 90nm CMOS with two different topologies. The front-end contains a transimpedance amplifier (TIA) and post amplifiers (PA) in 90 nm CMOS (Design 1) whereas in 65 nm CMOS (Design 2) an offset compensation block and a transconductor is incorporated to improve the robustness of the overall receiver front-end.The transimpedance amplifier in both designs is implemented with the shunt feedback topology and the post amplifiers in 90 nm and 65 nm design use the common source topology loaded with modified active inductors and the Cherry-Hooper inverter based topology, respectively. In order to make the receiver front-end power and bandwidth scalable, a current controlling PMOS array and a tuneable resistive bank is implemented in both designs. The Design 1 is able to vary the supported data rate from 1.25 Gb/s to 15 Gb/s. The gain at each data rate is ~ 84 dBΩ. The overall power dissipation varies from 0.94 mW to 7.46 mW as the data rate scales, maintaining an energy per bit lower than 800 fJ at all data rates using a 1.2 V power supply. The input referred noise density varies from 4.31 pA/√Hz to 14.27 pA/√Hz. In the Design 2, the receiver front-end can be tuned from 1.25 Gb/s to 20 Gb/s maintaining a fixed gain of ~75 dBΩ. The power dissipation in this case varies from 0.32 mW to 13.5 mW as the data rate scales up, maintaining energy per bit less than 700 fJ using a 1 V power supply. The input referred noise density varies from 8.46 pA/√Hz to 18 pA/√Hz. Simulation shows that Design 1 is not robust enough against the mismatch and global process variations whereas Design 2 is much more robust against these effects. This type of front-end has applications in links that vary data rate in response to system requirements. Additionally, the lowest data rate can be act as an idle mode which receives data used only to maintain transmitter and receiver synchronization

Design of a Transimpedance Amplifier for an Optical Receiver

In today’s world, technology is so developed that it is possible to transmit huge amounts of data in a short time. In the experiments with high energy levels in laboratories carried out in CERN, it is essential to have a method capable of carrying all this information and at the same time of being tolerant to the radiation from these same experiments. Optical fibres are currently the best method transmitting the data created by these experiments. In order to receive the information from the optical fibre a Photodiode (PD) is used to produce current from the light of the optical fibre. This current is however small. It is necessary to use an amplifier which, in addition to amplifying the current coming from the photodiode, also converts it into a voltage for the next phases of the optical receiver. These amplifiers are known as transimpedance amplifiers and are the critical part of optical receivers since an high gain is required to amplify the current from the photodiode and at the same time a high bandwidth to receive the hight data rate signals. This thesis presents a complete analysis of these amplifiers, showing various types of topologies and their pros and cons. In order to arrive at the amplifier with the desired characteristics, this thesis uses mathematical equations that allow us to describe the operation of the Transimpedance Amplifier (TIA) and to determine the optimal range between the gain, the bandwidth and the noise of the amplifier (input referred noise). All the theoretical expressions as well as the behaviour of the whole system was verified using electrical simulations

Distributed Circuit Analysis and Design for Ultra-wideband Communication and sub-mm Wave Applications

This thesis explores research into new distributed circuit design techniques and topologies, developed to extend the bandwidth of amplifiers operating in the mm and sub-mm wave regimes, and in optical and visible light communication systems. Theoretical, mathematical modelling and simulation-based studies are presented, with detailed designs of new circuits based on distributed amplifier (DA) principles, and constructed using a double heterojunction bipolar transistor (DHBT) indium phosphide (InP) process with fT =fmax of 350/600 GHz. A single stage DA (SSDA) with bandwidth of 345 GHz and 8 dB gain, based on novel techniques developed in this work, shows 140% bandwidth improvement over the conventional DA design. Furthermore, the matrix-single stage DA (M-SSDA) is proposed for higher gain than both the conventional DA and matrix amplifier. A two-tier M-SSDA with 14 dB gain at 300 GHz bandwidth, and a three-tier M-SSDA with a gain of 20 dB at 324 GHz bandwidth, based on a cascode gain cell and optimized for bandwidth and gain flatness, are presented based on full foundry simulation tests. Analytical and simulation-based studies of the noise performance peculiarities of the SSDA and its multiplicative derivatives are also presented. The newly proposed circuits are fabricated as monolithic microwave integrated circuits (MMICs), with measurements showing 7.1 dB gain and 200 GHz bandwidth for the SSDA and 12 dB gain at 170 GHz bandwidth for the three-tier M-SSDA. Details of layout, fabrication and testing; and discussion of performance limiting factors and layout optimization considerations are presented. Drawing on the concept of artificial transmission line synthesis in distributed amplification, a new technique to achieve up to three-fold improvement in the modulation bandwidth of light emitting diodes (LEDs) for visible light communication (VLC) is introduced. The thesis also describes the design and application of analogue pre-emphasis to improve signal-to-noise ratio in bandwidth limited optical transceivers

A Tesla-Blumlein PFL-Bipolar pulsed power generator

A Tesla-Blumlein PFL-Bipolar pulsed power generator, has been successfully designed, manufactured and demonstrated. The compact Tesla transformer that it employs has successfully charged capacitive loads to peak voltages up to 0.6 MV with an overall energy efficiency in excess of 90%. The Tesla driven Blumlein PFL generator is capable of producing a voltage impulse approaching 0.6 MV with a rise time close to 2 ns, generating a peak electrical power of up to 10 GW for 5 ns when connected to a 30 Ω resistive load. Potentially for medical application, a bipolar former has been designed and successfully implemented as an extension to the system and to enable the generation of a sinusoid-like voltage impulse with a peak-to-peak value reaching 650 kV and having a frequency bandwidth beyond 1 GHz. This thesis describes the application of various numerical techniques used to design a successful generator, such as filamentary modelling, electrostatic and transient (PSpice) circuit analysis, and Computer Simulation Technology (CST) simulation. All the major parameters of both the Tesla transformer, the Blumlein pulse forming line and the bipolar former were determined, enabling accurate modelling of the overall unit to be performed. The wide bandwidth and ultrafast embedded sensors used to monitor the dynamic characteristics of the overall system are also presented. Experimental results obtained during this major experimental programme are compared with theoretical predictions and the way ahead towards connecting to an antenna for medical application is considered

Characterization of process variability and robust optimization of analog circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 161-174).Continuous scaling of CMOS technology has enabled dramatic performance enhancement of CMOS devices and has provided speed, power, and density improvement in both digital and analog circuits. CMOS millimeter-wave applications operating at more than 50GHz frequencies has become viable in sub-100nm CMOS technologies, providing advantages in cost and high density integration compared to other heterogeneous technologies such as SiGe and III-V compound semiconductors. However, as the operating frequency of CMOS circuits increases, it becomes more difficult to obtain sufficiently wide operating ranges for robust operation in essential analog building blocks such as voltage-controlled oscillators (VCOs) and frequency dividers. The fluctuations of circuit parameters caused by the random and systematic variations in key manufacturing steps become more significant in nano-scale technologies. The process variation of circuit performance is quickly becoming one of the main concerns in high performance analog design. In this thesis, we show design and analysis of a VCO and frequency divider operating beyond 70GHz in a 65nm SOI CMOS technology. The VCO and frequency divider employ design techniques enlarging frequency operating ranges to improve the robustness of circuit operation. Circuit performance is measured from a number of die samples to identify the statistical properties of performance variation. A back-propagation of variation (BPV) scheme based on sensitivity analysis of circuit performance is proposed to extract critical circuit parameter variation using statistical measurement results of the frequency divider. We analyze functional failure caused by performance variability, and propose dynamic and static optimization methods to improve parametric yield. An external bias control is utilized to dynamically tune the divider operating range and to compensate for performance variation. A novel time delay model of a differential CML buffer is proposed to functionally approximate the maximum operating frequency of the frequency divider, which dramatically reduces computational cost of parametric yield estimation. The functional approximation enables the optimization of the VCO and frequency divider parametric yield with a reasonable amount of simulation time.by Daihyun Lim.Ph.D