An efficient modeling approach for substrate noise coupling analysis with multiple contacts in heavily doped CMOS processes

A computationally efficient and accurate substrate noise coupling model for multiple contacts in heavily doped CMOS processes is presented and validated with simulations and experimental data. The model is based on Z parameters that are scalable with contact separation and size. This results in fast extraction of substrate resistances for large circuit examples. The Z-parameter model can be readily extracted from three dimensional simulations or measured data. Extensions of the model to lightly doped substrates are also presented. Several examples demonstrate that this approach can be orders of magnitude faster than currently available techniques for substrate resistance extraction. The computed substrate resistances are in close agreement with the numerical simulations, with a maximum error less than 10%

Fast algorithms for ill-conditioned dense matrix problems in VLSI interconnect and substrate modeling

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (leaves 131-135).by Mike Chuan Chou.Ph.D

Packaging Design of IGBT Power Module Using Novel Switching Cells

Parasitic inductance in power modules generates voltage spikes and current ringing during switching which cause extra stress in power electronic devices, increase electromagnetic interference (EMI), and degrade the performance of the power converter system. As newer power devices have faster switching speeds and higher power ratings, the effect of the parasitic inductance of the power module is more pronounced. This dissertation proposes a novel packaging method for power electronics modules based on the concepts of novel switching cells: P-cell and N-cell. It can reduce the stray inductance in the current commutation path in a phase-leg module and hence improve the switching behavior. Taking an insulated gate bipolar transistor (IGBT) as an example, two phase-leg modules, specifically a conventional module and a P-cell and N-cell based module were designed. Using Ansoft Q3D Extractor, electromagnetic simulation was carried out to extract the stray inductance from the two modules. An ABB 1200 V / 75 A IGBT model and a diode model were built for simulation study. Circuit parasitics were extracted and modeled. Switching behavior with different package parasitics was studied based on the Saber simulation. Two prototype phase-leg modules were fabricated. The parasitics were measured using a precision impedance analyzer. The measurement results agree with the simulation very well. A double pulse tester was built in laboratory. Several approaches were used to reduce the circuit and measuring parasitics. From the switching characteristics of the two modules, it was verified that the larger stray inductance in the layout causes higher voltage overshoot during turn off, which in turn increases the turn off losses. Multichip (two in parallel) IGBT modules applying novel switching cells was also designed. The parasitics were extracted and compared to a conventional design. The overall loop inductance was reduced in the proposed module. However, the mismatch of the paralleled branches was larger

Energy-Efficient Wireless Interconnect Design for Non-Destructive Testing (NDT) Applications

A method for non-destructive, wireless testing of integrated circuits(ICs) is presented in this thesis. This system is suitable for applications which require testing after the manufacturing of ICs. According to Moore\u27s Law the number of transistors in an IC doubles every two years, the current probing equipment will also have to reduce its size accordingly which will be difficult after a certain point. The proposed system relies on near field communication in order to transfer data between probe and device under test. The probe and IC will include small antenna and a transceiver circuit. The antenna and the transceiver circuit can be integrated into the device without affecting the real estate and performance. Major advantages of non-destructive probing include no damage to the pads of test chip, higher test frequencies and less maintenance which will lead to higher pin densities. The antenna and transceiver circuit to be incorporated on the test chip are completely CMOS compliant.;The presented system here is a prototype which consists of a transceiver circuit along with an ultra-wideband antenna. The system was implemented in IBM 180nm CMOS process. The transceiver circuit communicates at a high frequency of 21.5GHz which in turn reduces the area consumed by the antenna and the transceiver circuit. The results obtained for our system show that an energy efficient wireless interconnect has been successfully implemented for future non-destructive testing applications

Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate resistances are accurate to about 10% of measurements. Advantages and limitations of several common measurement techniques used to measure substrate z-parameters and resistances are discussed. A new and accurate z-parameter based macro-model has been developed that can be used up to a few GHz for P⁺ for contacts that are as close as 2μm. This enhanced model also addresses the limitations of previous models with regards to implementation aspects and ease of integration in a CAD framework. Limitations of this modeling approach have been investigated. The calibration methodology can be used along with the scalable macromodel for a qualitative pre-design and pre-layout estimation of the digital switching noise that couples though the substrate to sensitive analog/RF circuits

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Realization of a low noise amplifier using 0.35 um SiGe-BicMOS Technology for IEEE 802.11a applications /

The trend demand for towards interactive multimedia services has forced the development of new wireless systems that has greater bandwidths. The evolution of current wireless communication systems has been very rapid. The main goal has been small-size and low-cost transceivers that can be designed for different applications. Data communication systems in compliant with IEEE 802.11a wireless local area network (WLAN) standard has found widespread use, meeting the market demands, for the last few years. Next generation WLAN operates in the 5-6 GHz frequency range. A front-end receiver capable of operating within this frequency range is essential to meet the current and future of products. One of the critical components, allowing the common use of the technology can be attributed to the high performance Low Noise Amplifiers (LNA) in the receiver chain of the 802.11a transceivers. In IEEE 802.11a, there are three frequency bands; 5.15GHz - 5.25GHz, 5.25GHz - 5.35GHz and 5.725GHz - 5.825GHz. In this thesis, we designed and fabricated a single-stage cascode amplifier with emitter inductive degeneration using 0.35 ´m-SiGe BiCMOS process for IEEE 802.11a receivers. The electromagnetic (EM) simulations of the passive components are performed by using Agilent MOMENTUM® tool and all the parasitic components are extracted and compensated, a crucial step for optimizing the performance parameters of the LNA. The simulation results are very similar to measurement results, confirming the effectiveness of design methodology provided in this work

An instruction systolic array architecture for multiple neural network types

Modern electronic systems, especially sensor and imaging systems, are beginning to incorporate their own neural network subsystems. In order for these neural systems to learn in real-time they must be implemented using VLSI technology, with as much of the learning processes incorporated on-chip as is possible. The majority of current VLSI implementations literally implement a series of neural processing cells, which can be connected together in an arbitrary fashion. Many do not perform the entire neural learning process on-chip, instead relying on other external systems to carry out part of the computation requirements of the algorithm. The work presented here utilises two dimensional instruction systolic arrays in an attempt to define a general neural architecture which is closer to the biological basis of neural networks - it is the synapses themselves, rather than the neurons, that have dedicated processing units. A unified architecture is described which can be programmed at the microcode level in order to facilitate the processing of multiple neural network types. An essential part of neural network processing is the neuron activation function, which can range from a sequential algorithm to a discrete mathematical expression. The architecture presented can easily carry out the sequential functions, and introduces a fast method of mathematical approximation for the more complex functions. This can be evaluated on-chip, thus implementing the entire neural process within a single system. VHDL circuit descriptions for the chip have been generated, and the systolic processing algorithms and associated microcode instruction set for three different neural paradigms have been designed. A software simulator of the architecture has been written, giving results for several common applications in the field

Modeling and design of matching-critical circuits

Existing approaches for modeling mismatch effects in matching-critical circuits are based upon models derived under the widely accepted premise that distributed parameter devices can be modeled with lumped parameter models. It is shown in this dissertation that the lumped parameter models do not consistently reflect device performance and introduce substantial errors in matching-critical circuits if either systematic or random parameter variations occur in the channel. A new approach for characterizing the effects of both systematic and random variations in semiconductor device properties on device matching is introduced. This approach circumvents the introduction of model errors inherent in the existing approaches. A CAD tool, MOSGRAD, was developed to simulate the effects of distributed two-dimensional systematic and random variations in device parameters on the performance of matching-critical circuits. The tool is capable of predicting the performance of non-conventional circuit structures in which multiple drain and/or source regions that may or may not be rectangular and/or multiply segmented. Through the use of the tool, new current mirror layout strategies have been developed that exhibit reduced sensitivity to matching in the presence of linear parameter gradients

NASA Tech Briefs Index 1980

Tech Briefs are short announcements of new technology derived from the research and development activities of the National Aeronautics and Space Administration. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This Index to NASA Tech Briefs contains abstracts and four indexes -- subject,. personal author, originating Center, and Tech Brief number -- for 1980 Tech Briefs