Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

Abstract

This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate resistances are accurate to about 10% of measurements. Advantages and limitations of several common measurement techniques used to measure substrate z-parameters and resistances are discussed. A new and accurate z-parameter based macro-model has been developed that can be used up to a few GHz for P⁺ for contacts that are as close as 2μm. This enhanced model also addresses the limitations of previous models with regards to implementation aspects and ease of integration in a CAD framework. Limitations of this modeling approach have been investigated. The calibration methodology can be used along with the scalable macromodel for a qualitative pre-design and pre-layout estimation of the digital switching noise that couples though the substrate to sensitive analog/RF circuits

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