A Capacitance-To-Digital Converter for MEMS Sensors for Smart Applications

The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 mu m CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm(2), which means a pressure resolution of 1 Pa, while consuming 146 mu A from a 1.5 V power supply.This work has been funded by Marie Curie project SIMIC, Grant Agreement No. 610484, funded by grants from the European Union (Research Executive Agency) and TEC2014-56879-R of CICYT, Spain.Publicad

Contribution to time domain readout circuits design for multi-standard sensing system for low voltage supply and high-resolution applications

Mención Internacional en el título de doctorThis research activity has the purpose of open new possibilities in the design of capacitance-to-digital converters (CDCs) by developing a solution based on time domain conversion. This can be applied to applications related with the Internet-of-Things (IoT). These applications are present in any electronic devices where sensing is needed. To be able to reduce the area of the whole system with the required performance, micro-electromechanical systems (MEMS) sensors are used in these applications. We propose a new family of sensor readout electronics to be integrated with MEMS sensors. Within the time domain converters, Dual Slope (DS) topology is very interesting to explore a new compromise between performances, area and power consumption. DS topology has been extensively used in instrumentation. The simplicity and robustness of the blocks inside classical DS converters it is the main advantage. However, they are not efficient for applications where higher bandwidth is required. To extend the bandwidth, DS converters have been introduced into ΔΣ loops. This topology has been named as integrating converters. They increase the bandwidth compare to classical DS architecture but at the expense of higher complexity. In this work we propose the use of a new family of DS converters that keep the advantages of the classical architecture and introduce noise shaping. This way the bandwidth is increased without extra blocks. The Self-Compensated noise-shaped DS converter (the name given to the new topology) keeps the signal transfer function (STF) and the noise transfer function (NTF) of Integrating converters. However, we introduce a new arrangement in the core of the converter to do noise shaping without extra circuitry. This way the simplicity of the architecture is preserved. We propose to use the Self-Compensated DS converter as a CDC for MEMS sensors. This work makes a study of the best possible integration of the two blocks to keep the signal integrity considering the electromechanical behavior of the sensor. The purpose of this front-end is to be connected to any kind of capacitive MEMS sensor. However, to prove the concepts developed in this thesis the architecture has been connected to a pressure MEMS sensor. An experimental prototype was implemented in 130-nm CMOS process using the architecture mentioned before. A peak SNR of 103.9 dB (equivalent to 1Pa) has been achieved within a time measurement of 20 ms. The final prototype has a power consumption of 220 μW with an effective area of 0.317 mm2. The designed architecture shows good performance having competitive numbers against high resolution topologies in amplitude domain.Esta actividad de investigación tiene el propósito de explorar nuevas posibilidades en el diseño de convertidores de capacitancia a digital (CDC) mediante el desarrollo de una solución basada en la conversión en el dominio del tiempo. Estos convertidores se pueden utilizar en aplicaciones relacionadas con el mercado del Internet-de-las-cosas (IoT). Hoy en día, estas aplicaciones están presentes en cualquier dispositivo electrónico donde se necesite sensar una magnitud. Para poder reducir el área de todo el sistema con el rendimiento requerido, se utilizan sensores de sistemas micro-electromecánicos (MEMS) en estas aplicaciones. Proponemos una nueva familia de electrónica de acondicionamiento para integrar con sensores MEMS. Dentro de los convertidores de dominio de tiempo, la topología del doble-rampa (DS) es muy interesante para explorar un nuevo compromiso entre rendimiento, área y consumo de energía. La topología de DS se ha usado ampliamente en instrumentación. La simplicidad y la solidez de los bloques dentro de los convertidores DS clásicos es la principal ventaja. Sin embargo, no son eficientes para aplicaciones donde se requiere mayor ancho de banda. Para ampliar el ancho de banda, los convertidores DS se han introducido en bucles ΔΣ. Esta topología ha sido nombrada como Integrating converters. Esta topología aumenta el ancho de banda en comparación con la arquitectura clásica de DS, pero a expensas de una mayor complejidad. En este trabajo, proponemos el uso de una nueva familia de convertidores DS que mantienen las ventajas de la arquitectura clásica e introducen la configuración del ruido. De esta forma, el ancho de banda aumenta sin bloques adicionales. El convertidor Self-Compensated noise-shaped DS (el nombre dado a la nueva topología) mantiene la función de transferencia de señal (STF) y la función de transferencia de ruido (NTF) de los Integrating converters. Sin embargo, presentamos una nueva topología en el núcleo del convertidor para conformar el ruido sin circuitos adicionales. De esta manera, se preserva la simplicidad de la arquitectura. Proponemos utilizar el Self-Compensated noise-shaped DS como un CDC para sensores MEMS. Este trabajo hace un estudio de la mejor integración posible de los dos bloques para mantener la integridad de la señal considerando el comportamiento electromecánico del sensor. El propósito de este circuito de acondicionamiento es conectarse a cualquier tipo de sensor MEMS capacitivo. Sin embargo, para demostrar los conceptos desarrollados en esta tesis, la arquitectura se ha conectado a un sensor MEMS de presión. Se ha implementado dos prototipos experimentales en un proceso CMOS de 130-nm utilizando la arquitectura mencionada anteriormente. Se ha logrado una relación señal-ruido máxima de 103.9 dB (equivalente a 1 Pa) con un tiempo de medida de 20 ms. El prototipo final tiene un consumo de energía de 220 μW con un área efectiva de 0.317 mm2. La arquitectura diseñada muestra un buen rendimiento comparable con las arquitecturas en el dominio de la amplitud que muestran resoluciones equivalentes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Pieter Rombouts.- Secretario: Alberto Rodríguez Pérez.- Vocal: Dietmar Strãußnig

12.8 kHz Energy-Efficient Read-Out IC for High Precision Bridge Sensor Sensing System

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 김수환.In the thesis, a high energy-efficient read-out integrated circuit (read-out IC) for a high-precision bridge sensor sensing system is proposed. A low-noise capacitively-coupled chopper instrumentation amplifier (CCIA) followed by a high-resolution incremental discrete-time delta-sigma modulator (DTΔΣΜ) analog-to-digital converter (ADC) is implemented. To increase energy-efficiency, CCIA is chosen, which has the highest energy-efficiency among IA types. CCIA has a programmable gain of 1 to 128 that can amplify the small output of the bridge sensor. Impedance boosting loop (IBL) is applied to compensate for the low input impedance, which is a disadvantage of a CCIA. Also, the sensor offset cancellation technique was applied to CCIA to eliminate the offset resulting from the resistance mismatch of the bridge sensor, and the bridge sensor offset from -350 mV to 350 mV can be eliminated. In addition, the output data rate of the read-out IC is designed to be 12.8 kHz to quickly capture data and to reduce the power consumption of the sensor by turning off the sensor and read-out IC for the rest of the time. Generally, bridge sensor system is much slower than 12.8 kHz. To suppress 1/f noise, system level chopping and correlated double sampling (CDS) techniques are used. Implemented in a standard 0.13-μm CMOS process, the ROIC’s effective resolution is 17.0 bits at gain 1 and that of 14.6 bits at gain 128. The analog part draws the average current of 139.4 μA from 3-V supply, and 60.2 μA from a 1.8 V supply.본 논문에서는 고정밀 브리지 센서 센싱 시스템을 위한 에너지 효율이 높은 Read-out Integrated Circuit (read-out IC)를 제안한다. 저 잡음 Capacitively-Coupled Instrumentation Amplifier (CCIA)에 이은 고해상도 Discrete-time Delta-Sigma 변조기(DTΔΣΜ) 아날로그-디지털 변환기(ADC)를 구현하였다. 에너지 효율을 높이기 위해 IA 유형 중 에너지 효율이 가장 높은 CCIA를 선택하였다. CCIA는 브리지 센서의 작은 출력을 증폭할 수 있는 1 에서 128의 프로그래밍 가능한 전압 이득을 가진다. CCIA의 단점인 낮은 입력 임피던스를 보상하기 위해 Impedance Boosting Loop (IBL)을 적용하였다. 또한 CCIA에 센서 오프셋 제거 기술을 적용하여 브리지 센서의 저항 미스매치로 인한 오프셋을 제거 기능을 탑재하였으며 -350mV에서 350mV까지 브리지 센서 오프셋을 제거할 수 있다. Read-out IC의 출력 데이터 전송률은 12.8kHz로 설계하여 데이터를 빠르게 채고 나머지 시간 동안 센서와 read-out IC를 꺼서 센서의 전력 소비를 줄일 수 있도록 설계하였다. 일반적으로 브리지 센서 시스템은 12.8kHz보다 느리기 때문에 이것이 가능하다. 하지만, 일반적인 CCIA는 입력 임피던스 때문에 빠른 속도에서 설계가 불가능하다. 이를 해결하기 위해 demodulate 차핑을 앰프 내부가 아닌 시스템 차핑을 이용해 해결하였다. 1/f 노이즈를 억제하기 위해 시스템 레벨 차핑 및 상관 이중 샘플링(CDS) 기술이 사용되었다. 0.13μm CMOS 공정에서 구현된 read-out IC의 Effective Resolution (ER)은 전압 이득 1에서 17.0비트이고 전압 이득 128에서 14.6비트를 달성하였다. 아날로그 회로는 3 V 전원에서 139.4μA의 평균 전류를, 디지털 회로는 1.8 V 전원에서 60.2μA의 평균 전류를 사용한다.CHAPTER 1 INTRODUCTION 1 1.1 SMART DEVICES 1 1.2 SMART SENSOR SYSTEMS 4 1.3 WHEATSTONE BRIDGE SENSOR 5 1.4 MOTIVATION 8 1.5 PREVIOUS WORKS 10 1.6 INTRODUCTION OF THE PROPOSED SYSTEM 14 1.7 THESIS ORGANIZATION 16 CHAPTER 2 SYSTEM OVERVIEW 17 2.1 SYSTEM ARCHITECTURE 17 CHAPTER 3 IMPLEMENTATION OF THE CCIA 19 3.1 CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER 19 3.2 IMPEDANCE BOOSTING 22 3.3 SENSOR OFFSET CANCELLATION 25 3.4 AMPLIFIER OFFSET CANCELLATION 29 3.5 AMPLIFIER IMPLEMENTATION 32 3.6 IMPLEMENTATION OF THE CCIA 35 CHAPTER 4 INCREMENTAL ΔΣ ADC 37 4.1 INTRODUCTION OF INCREMENTAL ΔΣ ADC 37 4.2 IMPLEMENTATION OF INCREMENTAL ΔΣ MODULATOR 40 CHAPTER 5 SYSTEM-LEVEL DESIGN 43 5.1 DIGITAL FILTER 43 5.2 SYSTEM-LEVEL CHOPPING & TIMING 46 CHAPTER 5 MEASUREMENT RESULTS 48 6.1 MEASUREMENT SUMMARY 48 6.2 LINEARITY & NOISE MEASUREMENT 51 6.3 SENSOR OFFSET CANCELLATION MEASUREMENT 57 6.4 INPUT IMPEDANCE MEASUREMENT 59 6.5 TEMPERATURE VARIATION MEASUREMENT 63 6.6 PERFORMANCE SUMMARY 66 CHAPTER 7 CONCLUSION 68 APPENDIX A. 69 ENERGY-EFFICIENT READ-OUT IC FOR HIGH-PRECISION DC MEASUREMENT SYSTEM WITH IA POWER REDUCTION TECHNIQUE 69 BIBLIOGRAPHY 83 한글초록 87박

A Low-Power Sigma-Delta Modulator for Healthcare and Medical Diagnostic Applications

This paper presents a switched-capacitor Sigma-Delta modulator designed in 90-nm CMOS technology, operating at 1.2-V supply voltage. The modulator targets healthcare and medical diagnostic applications where the readout of small-bandwidth signals is required. The design of the proposed A/D converter was optimized to achieve the minimum power consumption and area. A remarkable performance improvement is obtained through the integration of a low-noise amplifier with modified Miller compensation and rail-to-rail output stage. The manuscript also presents a set of design equations, from the small-signal analysis of the amplifier, for an easy design of the modulator in different technology nodes. The Sigma-Delta converter achieves a measured 96-dB dynamic range, over a 250-Hz signal bandwidth, with an oversampling ratio of 500. The power consumption is 30 μW, with a silicon area of 0.39 mm²

NASA's first in-space optical gyroscope: A technology experiment on the X ray Timing Explorer spacecraft

A technology experiment on the X-ray Timing Explorer spacecraft to determine the feasibility of Interferometric Fiber Optic Gyroscopes for space flight navigation is described. The experiment consists of placing a medium grade fiber optic gyroscope in parallel with the spacecraft's inertial reference unit. The performance of the fiber optic gyroscope will be monitored and compared to the primary mechanical gyroscope's performance throughout the two-year mission life

Delta-Sigma Modulator based Compact Sensor Signal Acquisition Front-end System

The proposed delta-sigma modulator ($\Delta\Sigma$M) based signal acquisition architecture uses a differential difference amplifier (DDA) customized for dual purpose roles, namely as instrumentation amplifier and as integrator of $\Delta\Sigma$M. The DDA also provides balanced high input impedance for signal from sensors. Further, programmable input amplification is obtained by adjustment of $\Delta\Sigma$M feedback voltage. Implementation of other functionalities, such as filtering and digitization have also been incorporated. At circuit level, a difference of transconductance of DDA input pairs has been proposed to reduce the effect of input resistor thermal noise of front-end R-C integrator of the $\Delta\Sigma$M. Besides, chopping has been used for minimizing effect of Flicker noise. The resulting architecture is an aggregation of functions of entire signal acquisition system within the single block of $\Delta\Sigma$M, and is useful for a multitude of dc-to-medium frequency sensing and similar applications that require high precision at reduced size and power. An implementation of this in 0.18-$\mu$m CMOS process has been presented, yielding a simulated peak signal-to-noise ratio of 80 dB and dynamic range of 109dBFS in an input signal band of 1 kHz while consuming 100 $\mu$W of power; with the measured signal-to-noise ratio being lower by about 9 dB.Comment: 13 pages, 16 figure

RF MEMS reference oscillators platform for wireless communications

A complete platform for RF MEMS reference oscillator is built to replace bulky quartz from mobile devices, thus reducing size and cost. The design targets LTE transceivers. A low phase noise 76.8 MHz reference oscillator is designed using material temperature compensated AlN-on-silicon resonator. The thesis proposes a system combining piezoelectric resonator with low loading CMOS cross coupled series resonance oscillator to reach state-of-the-art LTE phase noise specifications. The designed resonator is a two port fundamental width extensional mode resonator. The resonator characterized by high unloaded quality factor in vacuum is designed with low temperature coefficient of frequency (TCF) using as compensation material which enhances the TCF from - 3000 ppm to 105 ppm across temperature ranges of -40˚C to 85˚C. By using a series resonant CMOS oscillator, phase noise of -123 dBc/Hz at 1 kHz, and -162 dBc/Hz at 1MHz offset is achieved. The oscillator’s integrated RMS jitter is 106 fs (10 kHz–20 MHz), consuming 850 μA, with startup time is 250μs, achieving a Figure-of-merit (FOM) of 216 dB. Electronic frequency compensation is presented to further enhance the frequency stability of the oscillator. Initial frequency offset of 8000 ppm and temperature drift errors are combined and further addressed electronically. A simple digital compensation circuitry generates a compensation word as an input to 21 bit MASH 1 -1-1 sigma delta modulator incorporated in RF LTE fractional N-PLL for frequency compensation. Temperature is sensed using low power BJT band-gap front end circuitry with 12 bit temperature to digital converter characterized by a resolution of 0.075˚C. The smart temperature sensor consumes only 4.6 μA. 700 MHz band LTE signal proved to have the stringent phase noise and frequency resolution specifications among all LTE bands. For this band, the achieved jitter value is 1.29 ps and the output frequency stability is 0.5 ppm over temperature ranges from -40˚C to 85˚C. The system is built on 32nm CMOS technology using 1.8V IO device

Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation

Infrared imaging technology, used both to study deep-space bodies' radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm 2 chip integrated in a standard 0.18-μm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping, analog calibration, nor digital compensation technique. When coupled to a IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW